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0.13µm CMOS technology with optimized poly-Si / NO-oxide gate stack

dc.contributor.authorKubicek, Stefan
dc.contributor.authorJansen, Philippe
dc.contributor.authorBadenes, Gonçal
dc.contributor.authorSchaekers, Marc
dc.contributor.authorKol'dyaev, Victor
dc.contributor.authorDeferm, Ludo
dc.contributor.authorDe Meyer, Kristin
dc.contributor.authorKerr, Daniel
dc.contributor.authorNaem, Abdalla
dc.date.accessioned2021-10-06T11:34:22Z
dc.date.available2021-10-06T11:34:22Z
dc.date.issued1999
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/3576
dc.sourceIIOimport
dc.title0.13µm CMOS technology with optimized poly-Si / NO-oxide gate stack
dc.typeProceedings paper
dc.contributor.imecauthorKubicek, Stefan
dc.contributor.imecauthorSchaekers, Marc
dc.contributor.imecauthorDeferm, Ludo
dc.contributor.imecauthorDe Meyer, Kristin
dc.contributor.orcidimecSchaekers, Marc::0000-0002-1496-7816
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage193
dc.source.endpage202
dc.source.conferenceULSI Process Integration. Proceedings of the First International Symposium
dc.source.conferencedate17/10/1999
dc.source.conferencelocationHonolulu, HI USA
imec.availabilityPublished - open access
imec.internalnotesECS Proceedings; Vol. 99-18


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