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Optimization of wafer-level low-impedance contact CDM testers

dc.contributor.authorSimicic, Marko
dc.contributor.authorWu, Wei-Min
dc.contributor.authorJack, Nathan
dc.contributor.authorTamura, Shinichi
dc.contributor.authorShimada, Yohei
dc.contributor.authorSawada, Masanori
dc.contributor.authorChen, Shih-Hung
dc.date.accessioned2021-10-29T04:08:19Z
dc.date.available2021-10-29T04:08:19Z
dc.date.issued2020-11
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/35946
dc.sourceIIOimport
dc.titleOptimization of wafer-level low-impedance contact CDM testers
dc.typeProceedings paper
dc.contributor.imecauthorSimicic, Marko
dc.contributor.imecauthorWu, Wei-Min
dc.contributor.imecauthorChen, Shih-Hung
dc.contributor.orcidimecSimicic, Marko::0000-0002-3623-1842
dc.source.peerreviewyes
dc.source.conferenceEOS/ESD Symposium
dc.source.conferencedate13/09/2020
dc.source.conferencelocationReno, NV USA
dc.identifier.urlhttps://ieeexplore.ieee.org/document/9241215
imec.availabilityPublished - imec


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