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Evaluation of the impact of source/drain epi implementation on logic performance using combined process and circuit simulation

dc.contributor.authorSoussou, Assawer
dc.contributor.authorSchram, Tom
dc.contributor.authorMiyaguchi, Kenichi
dc.contributor.authorChakarov, Ivan
dc.contributor.authorParvais, Bertrand
dc.contributor.authorErvin, Joseph
dc.date.accessioned2021-10-29T04:37:49Z
dc.date.available2021-10-29T04:37:49Z
dc.date.issued2020
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/35996
dc.sourceIIOimport
dc.titleEvaluation of the impact of source/drain epi implementation on logic performance using combined process and circuit simulation
dc.typeProceedings paper
dc.contributor.imecauthorSoussou, Assawer
dc.contributor.imecauthorSchram, Tom
dc.contributor.imecauthorMiyaguchi, Kenichi
dc.contributor.imecauthorParvais, Bertrand
dc.contributor.orcidimecSchram, Tom::0000-0003-1533-7055
dc.contributor.orcidimecMiyaguchi, Kenichi::0000-0002-7073-6457
dc.contributor.orcidimecParvais, Bertrand::0000-0003-0769-7069
dc.source.peerreviewyes
dc.source.beginpageA-5-03
dc.source.conferenceInternational Conference on Solid State Devices and Materials - SSDM 2020
dc.source.conferencedate27/09/2020
dc.source.conferencelocationSan Francisco, CA USA
dc.identifier.urlhttps://confit.atlas.jp/guide/event/ssdm2020/subject/A-5-03/advanced?cryptoId=
imec.availabilityPublished - imec


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