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Interconnect Capacitance Investigation and Optimization Under I/O Pad for ESD Protection of RF/High Speed Circuits in Micro- & Nano-scale CMOS Technology

dc.contributor.authorWu, Wei-Min
dc.contributor.authorChen, Jie-Ting
dc.contributor.authorChen, Shih-Hung
dc.contributor.authorKer, Ming-Dou
dc.contributor.authorLinten, Dimitri
dc.contributor.authorGroeseneken, Guido
dc.date.accessioned2021-10-29T08:22:44Z
dc.date.available2021-10-29T08:22:44Z
dc.date.issued2020
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/36352
dc.sourceIIOimport
dc.titleInterconnect Capacitance Investigation and Optimization Under I/O Pad for ESD Protection of RF/High Speed Circuits in Micro- & Nano-scale CMOS Technology
dc.typeProceedings paper
dc.contributor.imecauthorWu, Wei-Min
dc.contributor.imecauthorChen, Shih-Hung
dc.contributor.imecauthorLinten, Dimitri
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.orcidimecLinten, Dimitri::0000-0001-8434-1838
dc.contributor.orcidimecGroeseneken, Guido::0000-0003-3763-2098
dc.source.peerreviewyes
dc.source.conference2020 International ESD Workshop (IEW)
dc.source.conferencedate4/05/2020
dc.source.conferencelocationJesteburg Germany
dc.identifier.urlhttps://www.esda.org/assets/Events/4cf93e2446/IEW-2020-program-1-3-2020.pdf
imec.availabilityPublished - imec


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