Edge-induced reliability & performance degradation in STT-MRAM: an etch engineering solution

Abstract

To enable high density STT-MRAM, process-induced damage needs to be minimized High temperature anneals and patterning can degrade performance and reliability. By employing a novel patterning scheme, involving physical ion beam etch, etchback and oxidation steps, we minimize the etch-induced damage and limit the oxygen penetration to the free layer, which can degrade device performance. Moreover, we demonstrate better magnetic properties, lower switching voltages and an improved reliability window. We establish BEOL compatibility with a 3-hour, 400 degrees C anneal at the end-of-line and study scaled MTJ arrays with physical diameter of 50 nm.