Cost-performance optimization of fine-pitch W2W bonding: functional system partitioning with heterogeneous FEOL/BEOL configurations

Abstract

Current Wafer-to-Wafer hybrid bonding process technology allows die stacking with 3D structure pitches in range of 1 mu m. Independent wafer processing prior to 3D stacking enables heterogeneous CMOS process integration, where each wafer FEOL, BEOL can be optimized for a given functionality to trade-off system performance and cost. Typical functional system partitioning aims the split of the system memory from the logic. While 3D structures with coarser pitches (e.g. micro-bumps) are already used to split the last-level cache (LLC) from the rest of the system (e.g. HBMs), finer 3D structures can be used to split lower and intermediate cache memory layers (L2, L1) from the core logic. System performance gets better since delay and cache latency can be reduced. Also the system cost can be reduced, since only the core layer is now built using the most expensive CMOS process. In this article we quantify the system-level post place & route performance and area benefits of Memory-on-Logic applications using advanced CMOS processes (< 10nm) for various BEOL configuration options, i.e. the number and geometrical properties of different metal layers used in the BEOL stack.