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Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node
dc.contributor.author | Gupta, A. | |
dc.contributor.author | Mertens, H. | |
dc.contributor.author | Tao, Z. | |
dc.contributor.author | Demuynck, S. | |
dc.contributor.author | Bommels, J. | |
dc.contributor.author | Arutchelvan, G. | |
dc.contributor.author | Devriendt, K. | |
dc.contributor.author | Pedreira, O. Varela | |
dc.contributor.author | Ritzenthaler, R. | |
dc.contributor.author | Wang, S. | |
dc.contributor.author | Radisic, D. | |
dc.contributor.author | Kenis, K. | |
dc.contributor.author | Teugels, L. | |
dc.contributor.author | Sebaai, F. | |
dc.contributor.author | Lorant, C. | |
dc.contributor.author | Jourdan, N. | |
dc.contributor.author | Chan, B. T. | |
dc.contributor.author | Zahedmanesh, H. | |
dc.contributor.author | Subramanian, S. | |
dc.contributor.author | Schleicher, F. | |
dc.contributor.author | Hopf, T. | |
dc.contributor.author | Peter, A. | |
dc.contributor.author | Rassoul, N. | |
dc.contributor.author | Debruyn, H. | |
dc.contributor.author | Demonie, I | |
dc.contributor.author | Siew, Y. | |
dc.contributor.author | Chiarella, T. | |
dc.contributor.author | Briggs, B. | |
dc.contributor.author | Zhou, D. | |
dc.contributor.author | Rosseel, E. | |
dc.contributor.author | De Keersgieter, A. | |
dc.contributor.author | Capogreco, E. | |
dc.contributor.author | Litta, E. Dentoni | |
dc.contributor.author | Boccardi, G. | |
dc.contributor.author | Baudot, S. | |
dc.contributor.author | Mannaert, G. | |
dc.contributor.author | Bontemps, N. | |
dc.contributor.author | Sepulveda, A. | |
dc.contributor.author | Mertens, S. | |
dc.contributor.author | Kim, M. S. | |
dc.contributor.author | Dupuy, E. | |
dc.contributor.author | Vandersmissen, K. | |
dc.contributor.author | Paolillo, S. | |
dc.contributor.author | Yakimets, D. | |
dc.contributor.author | Chehab, B. | |
dc.contributor.author | Favia, P. | |
dc.contributor.author | Drijbooms, C. | |
dc.contributor.author | Cousserier, J. | |
dc.contributor.author | Jaysankar, M. | |
dc.contributor.author | Lazzarino, F. | |
dc.contributor.author | Morin, P. | |
dc.contributor.author | Sanchez, E. | |
dc.contributor.author | Mitard, J. | |
dc.contributor.author | Wilson, C. | |
dc.contributor.author | Holsteyns, F. | |
dc.contributor.author | Tokei, Z. | |
dc.contributor.author | Horiguchi, N. | |
dc.date.accessioned | 2021-11-02T15:59:09Z | |
dc.date.available | 2021-11-02T15:59:09Z | |
dc.date.issued | 2020 | |
dc.identifier.issn | 0743-1562 | |
dc.identifier.other | WOS:000668063000097 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/37742 | |
dc.source | WOS | |
dc.title | Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node | |
dc.type | Proceedings paper | |
dc.contributor.imecauthor | Gupta, A. | |
dc.contributor.imecauthor | Mertens, H. | |
dc.contributor.imecauthor | Tao, Z. | |
dc.contributor.imecauthor | Demuynck, S. | |
dc.contributor.imecauthor | Bommels, J. | |
dc.contributor.imecauthor | Arutchelvan, G. | |
dc.contributor.imecauthor | Devriendt, K. | |
dc.contributor.imecauthor | Pedreira, O. Varela | |
dc.contributor.imecauthor | Ritzenthaler, R. | |
dc.contributor.imecauthor | Wang, S. | |
dc.contributor.imecauthor | Radisic, D. | |
dc.contributor.imecauthor | Kenis, K. | |
dc.contributor.imecauthor | Teugels, L. | |
dc.contributor.imecauthor | Sebaai, F. | |
dc.contributor.imecauthor | Lorant, C. | |
dc.contributor.imecauthor | Jourdan, N. | |
dc.contributor.imecauthor | Chan, B. T. | |
dc.contributor.imecauthor | Zahedmanesh, H. | |
dc.contributor.imecauthor | Subramanian, S. | |
dc.contributor.imecauthor | Schleicher, F. | |
dc.contributor.imecauthor | Hopf, T. | |
dc.contributor.imecauthor | Peter, A. | |
dc.contributor.imecauthor | Rassoul, N. | |
dc.contributor.imecauthor | Debruyn, H. | |
dc.contributor.imecauthor | Demonie, I | |
dc.contributor.imecauthor | Siew, Y. | |
dc.contributor.imecauthor | Chiarella, T. | |
dc.contributor.imecauthor | Briggs, B. | |
dc.contributor.imecauthor | Zhou, D. | |
dc.contributor.imecauthor | Rosseel, E. | |
dc.contributor.imecauthor | De Keersgieter, A. | |
dc.contributor.imecauthor | Capogreco, E. | |
dc.contributor.imecauthor | Litta, E. Dentoni | |
dc.contributor.imecauthor | Boccardi, G. | |
dc.contributor.imecauthor | Baudot, S. | |
dc.contributor.imecauthor | Mannaert, G. | |
dc.contributor.imecauthor | Bontemps, N. | |
dc.contributor.imecauthor | Sepulveda, A. | |
dc.contributor.imecauthor | Mertens, S. | |
dc.contributor.imecauthor | Kim, M. S. | |
dc.contributor.imecauthor | Dupuy, E. | |
dc.contributor.imecauthor | Vandersmissen, K. | |
dc.contributor.imecauthor | Paolillo, S. | |
dc.contributor.imecauthor | Yakimets, D. | |
dc.contributor.imecauthor | Chehab, B. | |
dc.contributor.imecauthor | Favia, P. | |
dc.contributor.imecauthor | Drijbooms, C. | |
dc.contributor.imecauthor | Cousserier, J. | |
dc.contributor.imecauthor | Jaysankar, M. | |
dc.contributor.imecauthor | Lazzarino, F. | |
dc.contributor.imecauthor | Morin, P. | |
dc.contributor.imecauthor | Sanchez, E. | |
dc.contributor.imecauthor | Mitard, J. | |
dc.contributor.imecauthor | Wilson, C. | |
dc.contributor.imecauthor | Holsteyns, F. | |
dc.contributor.imecauthor | Tokei, Z. | |
dc.contributor.imecauthor | Horiguchi, N. | |
dc.identifier.eisbn | 978-1-7281-6460-1 | |
dc.source.numberofpages | 2 | |
dc.source.peerreview | yes | |
dc.source.conference | IEEE Symposium on VLSI Technology and Circuits | |
dc.source.conferencedate | JUN 15-19, 2020 | |
imec.availability | Under review |
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