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Addressing Key Challenges for SiGe-pFin Technologies: Fin Integrity, Low-D-IT Si-cap-free Gate Stack and Optimizing the Channel Strain

dc.contributor.authorArimura, Hiroaki
dc.contributor.authorCapogreco, Elena
dc.contributor.authorWostyn, Kurt
dc.contributor.authorEneman, Geert
dc.contributor.authorRagnarsson, Lars-Ake
dc.contributor.authorBrus, Stephan
dc.contributor.authorBaudot, Sylvain
dc.contributor.authorPeter, Antony
dc.contributor.authorSchram, Tom
dc.contributor.authorFavia, Paola
dc.contributor.authorRichard, Olivier
dc.contributor.authorBender, Hugo
dc.contributor.authorMitard, Jerome
dc.contributor.authorHoriguchi, Naoto
dc.date.accessioned2021-12-14T09:46:41Z
dc.date.available2021-11-02T15:59:09Z
dc.date.available2021-12-14T09:46:41Z
dc.date.issued2020
dc.identifier.issn0743-1562
dc.identifier.otherWOS:000668063000024
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/37746.2
dc.sourceWOS
dc.titleAddressing Key Challenges for SiGe-pFin Technologies: Fin Integrity, Low-D-IT Si-cap-free Gate Stack and Optimizing the Channel Strain
dc.typeProceedings paper
dc.contributor.imecauthorArimura, H.
dc.contributor.imecauthorCapogreco, E.
dc.contributor.imecauthorWostyn, K.
dc.contributor.imecauthorEneman, G.
dc.contributor.imecauthorRagnarsson, L. A.
dc.contributor.imecauthorBrus, S.
dc.contributor.imecauthorBaudot, S.
dc.contributor.imecauthorPeter, A.
dc.contributor.imecauthorSchram, T.
dc.contributor.imecauthorFavia, P.
dc.contributor.imecauthorRichard, O.
dc.contributor.imecauthorBender, H.
dc.contributor.imecauthorMitard, J.
dc.contributor.imecauthorHoriguchi, N.
dc.contributor.imecauthorArimura, Hiroaki
dc.contributor.imecauthorCapogreco, Elena
dc.contributor.imecauthorWostyn, Kurt
dc.contributor.imecauthorEneman, Geert
dc.contributor.imecauthorRagnarsson, Lars-Ake
dc.contributor.imecauthorBrus, Stephan
dc.contributor.imecauthorBaudot, Sylvain
dc.contributor.imecauthorPeter, Antony
dc.contributor.imecauthorSchram, Tom
dc.contributor.imecauthorFavia, Paola
dc.contributor.imecauthorRichard, Olivier
dc.contributor.imecauthorBender, Hugo
dc.contributor.imecauthorMitard, Jerome
dc.contributor.imecauthorHoriguchi, Naoto
dc.contributor.orcidimecWostyn, Kurt::0000-0003-3995-0292
dc.contributor.orcidimecEneman, Geert::0000-0002-5849-3384
dc.contributor.orcidimecRagnarsson, Lars-Ake::0000-0003-1057-8140
dc.contributor.orcidimecSchram, Tom::0000-0003-1533-7055
dc.contributor.orcidimecFavia, Paola::0000-0002-1019-3497
dc.contributor.orcidimecRichard, Olivier::0000-0002-3994-8021
dc.contributor.orcidimecMitard, Jerome::0000-0002-7422-079X
dc.contributor.orcidimecHoriguchi, Naoto::0000-0001-5490-0416
dc.identifier.eisbn978-1-7281-6460-1
dc.source.numberofpages2
dc.source.peerreviewyes
dc.source.conferenceIEEE Symposium on VLSI Technology and Circuits
dc.source.conferencedateJUN 15-19, 2020
dc.source.conferencelocationHonolulu, HI, USA
dc.source.journalna
imec.availabilityPublished - imec


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220.500.12860/37746.2*2021-12-14T09:40:07Zvalidation by library/open access desk
120.500.12860/377462021-11-02T15:59:09Z

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