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Addressing Key Challenges for SiGe-pFin Technologies: Fin Integrity, Low-D-IT Si-cap-free Gate Stack and Optimizing the Channel Strain
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Authors
Arimura, Hiroaki
;
Capogreco, Elena
;
Wostyn, Kurt
;
Eneman, Geert
;
Ragnarsson, Lars-Ake
;
Brus, Stephan
;
Baudot, Sylvain
;
Peter, Antony
;
Schram, Tom
;
Favia, Paola
;
Richard, Olivier
;
Bender, Hugo
;
Mitard, Jerome
;
Horiguchi, Naoto
EISBN
978-1-7281-6460-1
ISSN
0743-1562
Conference
IEEE Symposium on VLSI Technology and Circuits
Journal
na
Title
Addressing Key Challenges for SiGe-pFin Technologies: Fin Integrity, Low-D-IT Si-cap-free Gate Stack and Optimizing the Channel Strain
Publication type
Proceedings paper
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Date
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2
20.500.12860/37746.2
*
2021-12-14T09:40:07Z
validation by library/open access desk
1
20.500.12860/37746
2021-11-02T15:59:09Z
*Selected version
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