Browsing by author "Horiguchi, Naoto"
Now showing items 1-20 of 444
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1.5×10-9 Ω·cm² Contact Resistivity on Highly Doped Si:P Using Ge Pre-amorphization and Ti Silicidation
Yu, Hao; Schaekers, Marc; Rosseel, Erik; Peter, Antony; Lee, Joon-Gon; Song, Woo-Bin; Demuynck, Steven; Chiarella, Thomas; Ragnarsson, Lars-Ake; Kubicek, Stefan; Everaert, Jean-Luc; Horiguchi, Naoto; Barla, Kathy; Kim, Daeyong; Collaert, Nadine; Thean, Aaron; De Meyer, Kristin (2015) -
1/f noise analysis of replacement metal gate bulk p-type fin field effect transistor
Lee, Jae Woo; Cho, Moon Ju; Simoen, Eddy; Ritzenthaler, Romain; Togo, Mitsuhiro; Boccardi, Guillaume; Mitard, Jerome; Ragnarsson, Lars-Ake; Chiarella, Thomas; Veloso, Anabela; Horiguchi, Naoto; Thean, Aaron; Groeseneken, Guido (2013-03) -
15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process
Mitard, Jerome; Witters, Liesbeth; Loo, Roger; Lee, Seung Hun; Sun, J.W.; Franco, Jacopo; Ragnarsson, Lars-Ake; Brand, A.; Lu, X.; Yoshido, N.; Eneman, Geert; Brunco, David; Vorderwestner, M.; Storck, P.; Milenin, Alexey; Hikavyy, Andriy; Waldron, Niamh; Favia, Paola; Vanhaeren, Danielle; Vanderheyden, Annelies; Richard, Olivier; Mertens, Hans; Arimura, Hiroaki; Sioncke, Sonja; Vrancken, Christa; Bender, Hugo; Eyben, Pierre; Barla, Kathy; Lee, Sun Ghil; Horiguchi, Naoto; Collaert, Nadine; Thean, Aaron (2014) -
1mA/μm-ION strained SiGe45%-IFQW pFETs with raised and embedded S/D
Mitard, Jerome; Witters, Liesbeth; Hellings, Geert; Krom, Raymond; Franco, Jacopo; Eneman, Geert; Hikavyy, Andriy; Vincent, Benjamin; Loo, Roger; Favia, Paola; Dekkers, Harold; Altamirano Sanchez, Efrain; Vanderheyden, Annelies; Vanhaeren, Danielle; Eyben, Pierre; Takeoka, Shinji; Yamaguchi, Shinpei; Van Dal, Mark; Wang, Wei-E; Hong, Sug-Hun; Vandervorst, Wilfried; De Meyer, Kristin; Biesemans, Serge; Absil, Philippe; Horiguchi, Naoto; Hoffmann, Thomas Y. (2011) -
2D and 3D Fully-depleted extension-less devices for advanced logic and memory applications
Veloso, Anabela; De Keersgieter, An; Aoulaiche, Marc; Jurczak, Gosia; Thean, Aaron; Horiguchi, Naoto (2012-09) -
3D FinFET gate etch for advanced CMOS scaling
Dupuy, Emmanuel; Altamirano Sanchez, Efrain; Marinov, Daniil; Hody, Hubert; Mertens, Hans; Siew, Yong Kong; Demuynck, Steven; Horiguchi, Naoto (2019) -
3D sequential CMOS top tier devices demonstration using a low temperature Smart Cu (TM) Si layer transfer
Besnard, Guillaume; Radu, Ionut; Vandooren, Anne; Wu, Zhicheng; Franco, Jacopo; Li, Waikin; Arimura, Hiroaki; Mannaert, Geert; Rosseel, Erik; Hikavyy, Andriy; Dentoni Litta, Eugenio; Horiguchi, Naoto (2021) -
3D sequential low temperature top tier devices using dopant activation with excimer laser anneal and strained silicon as performance boosters
Vandooren, Anne; Wu, Zhicheng; Parihar, Narendra; Franco, Jacopo; Parvais, Bertrand; Matagne, Philippe; Debruyn, Haroen; Mannaert, Geert; Devriendt, Katia; Teugels, Lieve; Vecchio, Emma; Radisic, Dunja; Rosseel, Erik; Hikavyy, Andriy; Chan, BT; Waldron, Niamh; Mitard, Jerome; Besnard, G.; Alvarez, A.; Gaudin, G.; Schwarzenbach, W.; Radu, I.; Nguyen, B. Y.; Huet, K.; Tabata, T.; Mazzamuto, F.; Demuynck, Steven; Boemmels, Juergen; Collaert, Nadine; Horiguchi, Naoto (2020) -
3D simulation for melt laser anneal integration in FinFET's contact
Tabata, Toshiyuki; Curvers, Benoit; Huet, Karim; Chew, Soon Aik; Everaert, Jean-Luc; Horiguchi, Naoto (2020) -
3D-carrier profiling and parasitic resistance analysis in vertically stacked gate-all-around Si nanowire CMOS transistors
Eyben, Pierre; Ritzenthaler, Romain; De Keersgieter, An; Chiarella, Thomas; Veloso, Anabela; Mertens, Hans; Pena, Vanessa; Santoro, Gaetano; Machillot, Jerome; Kim, Myungsun; Miyashita, Toshihiko; Yoshida, Naomi; Bender, Hugo; Richard, Olivier; Celano, Umberto; Paredis, Kristof; Wouters, Lennaert; Mitard, Jerome; Horiguchi, Naoto (2019) -
3D-carrier profiling in FinFETs using scanning spreading resistance microscopy
Mody, Jay; Zschaetzsch, Gerd; Koelling, Sebastian; De Keersgieter, An; Eneman, Geert; Kambham, Ajay Kumar; Drijbooms, Chris; Schulze, Andreas; Chiarella, Thomas; Horiguchi, Naoto; Hoffmann, Thomas; Eyben, Pierre; Vandervorst, Wilfried (2011) -
80 nm tall thermally stable cost effective FinFETs for advanced dynamic random access memory periphery devices for artificial intelligence/machine learning and automotive applications
Spessot, Alessio; Ritzenthaler, Romain; Dentoni Litta, Eugenio; Dupuy, Emmanuel; O'Sullivan, Barry; Bastos, Joao; Capogreco, Elena; Miyaguchi, Kenichi; Machkaoutsan, Vladimir; Yoon, Younggwang; Fazan, Pierre; Horiguchi, Naoto (2021) -
80nm tall thermally stable cost effective FinFETs for advanced DRAM periphery devices for AI/ML and Automotive applications
Spessot, Alessio; Ritzenthaler, Romain; Dentoni Litta, Eugenio; Dupuy, Emmanuel; O'Sullivan, Barry; Bastos, Joao; Capogreco, Elena; Miyaguchi, Kenichi; Machkaoutsan, Vladimir; Yoon, Younggwang; Fazan, Pierre; Horiguchi, Naoto (2020) -
85nm-wide 1.5mA/μm-ION IFQW SiGe-pFET: raised vs embedded Si0.75Ge0.25 S/D benchmarking and in-depth hole transport study
Mitard, Jerome; Witters, Liesbeth; Eneman, Geert; Hellings, Geert; Pantisano, Luigi; Hikavyy, Andriy; Loo, Roger; Eyben, Pierre; Horiguchi, Naoto; Thean, Aaron (2012) -
A 2nd generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si-channel FinFETs
Mitard, Jerome; Witters, Liesbeth; Sasaki, Yuichiro; Arimura, Hiroaki; Schulze, Andreas; Loo, Roger; Ragnarsson, Lars-Ake; Hikavyy, Andriy; Cott, Daire; Chiarella, Thomas; Kubicek, Stefan; Mertens, Hans; Ritzenthaler, Romain; Vrancken, Christa; Favia, Paola; Bender, Hugo; Horiguchi, Naoto; Barla, Kathy; Mocuta, Dan; Mocuta, Anda; Collaert, Nadine; Thean, Aaron (2016-06) -
A comparison of arsenic and phosphorus extension by room temperature and hot ion implantation for NMOS Si bulk-FinFET at N7 (7nm) technology relevant fin dimensions
Sasaki, Yuichiro; Ritzenthaler, Romain; De Keersgieter, An; Chiarella, Thomas; Kubicek, Stefan; Rosseel, Erik; Waite, Andrew; del Agua Borniquel, Jose Ignacio; Colombeau, Benjamin; Chew, Soon Aik; Kim, Min-Soo; Schram, Tom; Demuynck, Steven; Vandervorst, Wilfried; Horiguchi, Naoto; Mocuta, Dan; Mocuta, Anda; Thean, Aaron (2015-06) -
A DRAM compatible Cu contact using self-aligned Ta-silicide and Ta-barrier
Zhao, Chao; Ahn, Jae Young; Horiguchi, Naoto; Demuynck, Steven; Tokei, Zsolt (2008) -
A low-power HKMG CMOS platform compatible with DRAM node 2x and beyond
Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; Caillat, Christian; Aoulaiche, Marc; Cho, Moon Ju; Noh, Kyung Bong; Son, Yunik; Na, Hoon Jo; Kauerauf, Thomas; Douhard, Bastien; Nazir, Aftab; Chew, Soon Aik; Milenin, Alexey; Altamirano Sanchez, Efrain; Schoofs, Geert; Albert, Johan; Sebaai, Farid; Vecchio, Emma; Paraschiv, Vasile; Vandervorst, Wilfried; Lee, Sun Ghil; Collaert, Nadine; Fazan, Pierre; Horiguchi, Naoto; Thean, Aaron (2014) -
A low-voltage biasing scheme for aggressively scaled bulk FinFET 1T-DRAM featuring 10s retention at 85°C
Collaert, Nadine; Aoulaiche, Marc; De Wachter, Bart; Rakowski, Michal; Redolfi, Augusto; Brus, Stephan; De Keersgieter, An; Horiguchi, Naoto; Altimime, Laith; Jurczak, Gosia (2010) -
A new high-k/metal gate CMOS integration scheme (Diffusion and Gate Replacement) suppressing gate height asymmetry and compatible with high-thermal budget memory technologies
Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; Caillat, Christian; Cho, Moon Ju; Simoen, Eddy; Aoulaiche, Marc; Albert, Johan; Chew, Soon Aik; Noh, Kyung Bong; Son, Yunik; Fazan, Pierre; Horiguchi, Naoto; Thean, Aaron (2014)