Browsing by author "Baudot, Sylvain"
Now showing items 1-17 of 17
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Addressing Key Challenges for SiGe-pFin Technologies: Fin Integrity, Low-D-IT Si-cap-free Gate Stack and Optimizing the Channel Strain
Arimura, Hiroaki; Capogreco, Elena; Wostyn, Kurt; Eneman, Geert; Ragnarsson, Lars-Ake; Brus, Stephan; Baudot, Sylvain; Peter, Antony; Schram, Tom; Favia, Paola; Richard, Olivier; Bender, Hugo; Mitard, Jerome; Horiguchi, Naoto (2020) -
Buried power rail integration with FinFETs for ultimate CMOS scaling
Gupta, Anshul; Varela Pedreira, Olalla; Arutchelvan, Goutham; Zahedmanesh, Houman; Devriendt, Katia; Hanssen, Frederik; Tao, Zheng; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Dentoni Litta, Eugenio; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, Noemie; Sepulveda Marquez, Alfonso; Mertens, Sofie; Kim, Min-Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Cousserier, Joris; Yakimets, Dmitry; Lazzarino, Frederic; Chehab, Bilal; Favia, Paola; Drijbooms, Chris; Jaysankar, Manoj; Morin, Pierre; Altamirano Sanchez, Efrain; Mitard, Jerome; Wilson, Chris; Holsteyns, Frank; Boemmels, Juergen; Demuynck, Steven; Tokei, Zsolt; Horiguchi, Naoto (2020) -
Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node
Gupta, Anshul; Mertens, Hans; Tao, Zheng; Demuynck, Steven; Boemmels, Juergen; Arutchelvan, Goutham; Devriendt, Katia; Varela Pedreira, Olalla; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Zahedmanesh, Houman; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Dentoni Litta, Eugenio; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, N.; Sepulveda Marquez, Alfonso; Mertens, Sofie; Kim, Min Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Yakimets, Dmitry; Chehab, Bilal; Favia, Paola; Drijbooms, Chris; Cousserier, Joris; Jaysankar, Manoj; Lazzarino, Frederic; Morin, Pierre; Altamirano Sanchez, Efrain; Mitard, Jerome; Wilson, Chris; Holsteyns, Frank; Tokei, Zsolt; Horiguchi, Naoto (2020) -
Channel Length Dependence of PBTI in High-k First RMG Gate Stack Integration Scheme
Parihar, Narendra; Arutchelvan, Goutham; Franco, Jacopo; Baudot, Sylvain; Opdebeeck, Ann; Demuynck, Steven; Arimura, Hiroaki; Ragnarsson, Lars-Ake; Mitard, Jerome; De Heyn, Vincent; Mercha, Abdelkarim (2021) -
Cleaning the high aspect ratio STI structures for advanced logic devices by implementation of a surface modification drying technique
Sebaai, Farid; Vereecke, Guy; Xu, XiuMei; Baudot, Sylvain; Amemiya, Fumihiro; Komori, Kana; Holsteyns, Frank (2018) -
Cumulated charging mechanisms at gate processing in high-kappa first planar NMOS devices
Hiblot, Gaspard; Parihar, Narendra; Dupuy, Emmanuel; Mannaert, Geert; Baudot, Sylvain; Kaczer, Ben; De Heyn, Vincent; Mercha, Abdelkarim (2020) -
Engineering high quality and conformal ultrathin SiNx films by PEALD for downscaled and advanced CMOS nodes
Tomomi, Takayama; Taishi, Ebisudani; Eiichiro, Shiba; Sepulveda Marquez, Alfonso; Blanquart, Timothee; Kimura, Yosuke; Subramanian, Sujith; Baudot, Sylvain; Briggs, Basoene; Gupta, Anshul; Veloso, Anabela; Capogreco, Elena; Mertens, Hans; Meersschaut, Johan; Conard, Thierry; Dara, Praveen; Geypen, Jef; Martinez Alanis, Gerardo Tadeo; Batuk, Dmitry; Demuynck, Steven; Morin, Pierre (2021) -
First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers
Subramanian, Sujith; Hosseini, Maryam; Chiarella, Thomas; Sarkar, Satadru; Schuddinck, Pieter; Chan, BT; Radisic, Dunja; Mannaert, Geert; Hikavyy, Andriy; Rosseel, Erik; Sebaai, Farid; Peter, Antony; Hopf, Toby; Morin, Pierre; Wang, Shouhua; Devriendt, Katia; Batuk, Dmitry; Martinez Alanis, Gerardo Tadeo; Veloso, Anabela; Dentoni Litta, Eugenio; Baudot, Sylvain; Siew, Yong Kong; Zhou, X.; Briggs, Basoene; Capogreco, Elena; Hung, Joey; Koret, R.; Spessot, Alessio; Ryckaert, Julien; Demuynck, Steven; Horiguchi, Naoto; Boemmels, Juergen (2020) -
N7 FinFET self-aligned quadruple patterning modeling
Baudot, Sylvain; Guissi, Sofiane; Milenin, Alexey; Ervin, Joe; Schram, Tom (2018) -
New bending mode in SAQP Si fins and its mitigation
Sepulveda Marquez, Alfonso; Hellin, David; Zhang, Liping; Kenis, Karine; Batuk, Dmitry; Baudot, Sylvain; Briggs, Basoene; Mountsier, Tom; Barla, Kathy; Morin, Pierre; Altamirano Sanchez, Efrain (2022) -
Plasma Charging Damage in HK-First and HK-Last RMG NMOS Devices
Hiblot, Gaspard; Parihar, Narendra; Dupuy, Emmanuel; Mannaert, Geert; Baudot, Sylvain; Kaczer, Ben; Franco, Jacopo; Vandooren, Anne; De Heyn, Vincent; Mercha, Abdelkarim (2021) -
Process variation analysis of device performance using virtual fabrication: methodology demonstrated on a CMOS 14-nm FinFET vehicle
Vincent, Benjamin; Hathwar, R.; Kamon, M.; Ervin, J.; Schram, Tom; Chiarella, Thomas; Demuynck, Steven; Baudot, Sylvain; Siew, Yong Kong; Kubicek, Stefan; Dentoni Litta, Eugenio; Chew, Soon Aik; Mitard, Jerome (2020) -
Self-aligned fin cut last patterning scheme for fin arrays of 24nm pitch and beyond
Baudot, Sylvain; Soussou, Assawer; Milenin, Alexey; Hopf, Toby; Wang, Shouhua; Weckx, Pieter; Vincent, Benjamin; Ervin, Joe; Demuynck, Steven (2019) -
Self-aligned fin cut last patterning scheme for fin arrays of 24nm pitch and beyond
Baudot, Sylvain; Soussou, Assawer; Milenin, Alexey; Ervin, Joe; Demuynck, Steven (2018) -
Very low temperature epitaxy of group-IV semiconductors for use in finFET, stacked nanowires and monolithic 3D integration
Porret, Clément; Hikavyy, Andriy; Gomez Granados, Juan Fernando; Baudot, Sylvain; Vohra, Anurag; Kunert, Bernardette; Douhard, Bastien; Bogdanowicz, Janusz; Schaekers, Marc; Kohen, David; Margetis, Joe; Tolle, John; Petersen Lima, Lucas; Sammak, Amir; Scappucci, Giordano; Rosseel, Erik; Langer, Robert; Loo, Roger (2018) -
Very low temperature epitaxy of group-IV semiconductors for use in FinFET, stacked nanowires and monolithic 3D integration
Porret, Clément; Hikavyy, Andriy; Gomez Granados, Juan Fernando; Baudot, Sylvain; Vohra, Anurag; Kunert, Bernardette; Douhard, Bastien; Bogdanowicz, Janusz; Schaekers, Marc; Kohen, David; Margetis, Joe; Tolle, John; Petersen Barbosa Lima, Lucas; Sammak, Amir; Scappucci, Giordano; Rosseel, Erik; Langer, Robert; Loo, Roger (2018) -
Very low temperature epitaxy of group-IV semiconductors for use in FinFET, stacked nanowires and monolithic 3D integration
Porret, Clément; Hikavyy, Andriy; Gomez Granados, Fernando; Baudot, Sylvain; Vohra, Anurag; Kunert, Bernardette; Douhard, Bastien; Bogdanowicz, Janusz; Schaekers, Marc; Kohen, David; Margetis, Joe; Tolle, John; Petersen Lima, Lucas; Sammak, Amir; Scappucci, Giordano; Rosseel, Erik; Langer, Robert; Loo, Roger (2019)