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Addressing Key Challenges for SiGe-pFin Technologies: Fin Integrity, Low-D-IT Si-cap-free Gate Stack and Optimizing the Channel Strain

dc.contributor.authorArimura, H.
dc.contributor.authorCapogreco, E.
dc.contributor.authorWostyn, K.
dc.contributor.authorEneman, G.
dc.contributor.authorRagnarsson, L. A.
dc.contributor.authorBrus, S.
dc.contributor.authorBaudot, S.
dc.contributor.authorPeter, A.
dc.contributor.authorSchram, T.
dc.contributor.authorFavia, P.
dc.contributor.authorRichard, O.
dc.contributor.authorBender, H.
dc.contributor.authorMitard, J.
dc.contributor.authorHoriguchi, N.
dc.date.accessioned2021-11-02T15:59:09Z
dc.date.available2021-11-02T15:59:09Z
dc.date.issued2020
dc.identifier.issn0743-1562
dc.identifier.otherWOS:000668063000024
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/37746
dc.sourceWOS
dc.titleAddressing Key Challenges for SiGe-pFin Technologies: Fin Integrity, Low-D-IT Si-cap-free Gate Stack and Optimizing the Channel Strain
dc.typeProceedings paper
dc.contributor.imecauthorArimura, H.
dc.contributor.imecauthorCapogreco, E.
dc.contributor.imecauthorWostyn, K.
dc.contributor.imecauthorEneman, G.
dc.contributor.imecauthorRagnarsson, L. A.
dc.contributor.imecauthorBrus, S.
dc.contributor.imecauthorBaudot, S.
dc.contributor.imecauthorPeter, A.
dc.contributor.imecauthorSchram, T.
dc.contributor.imecauthorFavia, P.
dc.contributor.imecauthorRichard, O.
dc.contributor.imecauthorBender, H.
dc.contributor.imecauthorMitard, J.
dc.contributor.imecauthorHoriguchi, N.
dc.identifier.eisbn978-1-7281-6460-1
dc.source.numberofpages2
dc.source.peerreviewyes
dc.source.conferenceIEEE Symposium on VLSI Technology and Circuits
dc.source.conferencedateJUN 15-19, 2020
imec.availabilityUnder review


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220.500.12860/37746.22021-12-14T09:40:07Zvalidation by library/open access desk
120.500.12860/37746*2021-11-02T15:59:09Z

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