Extreme Wafer Thinning and nano-TSV processing for 3D Heterogeneous Integration

Abstract

This paper presents a novel approach for extreme wafer thinning on carrier followed by nano-scale via-last formation in order to achieve sub-500nm pitch interconnects, electrically connecting the backside to the frontside of a device wafer. Indeed, it is expected that most of the 3D System-on-Chip (3D-SOC) integration technology schemes will require a wafer-to-wafer (W2W) bonding approach, combined with via-last TSV (Through Silicon Vias) connections. To reach sub-500nm interconnect pitches, via-last TSV scaling is also expected to follow a similar trend. To do so, a dedicated sub-micron wafer thinning process was developed that enables a very tight thickness control over the entire wafer, with less than 70nm total thickness variation (TTV), and nano-TSV's were etched using a Bosch process applied to extremely small CD structures (180x250nm top CD). Functional electrical structures have been measured and characterized, showing up to 99% electrical yielding connections between frontside and backside of the device wafers.