Thermal, Mechanical and Reliability assessment of Hybrid bonded wafers, bonded at 2.5 mu m pitch

Abstract

In this paper we address the thermal, mechanical and reliability performance of wafer-to-wafer hybrid bonded CMOS wafers manufactured using standard 65nm technology. Proprietary chip design includes different test structures which enable assessment of hybrid interconnect yield and mechanical induced stress as well as thermal measurements with high spatial resolution. Different tests are conducted to reproduce thermo-mechanical stresses similar to the ones induced in flip-chip assemblies. The study, supported by the finite element simulations includes hot-spot thermal analysis where thermal resistance of hybrid interface is evaluated and the heat spreading effect in both wafers is compared.