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High performance raised gate/source/drain transistors for sub-0.15 μm CMOS technologies

dc.contributor.authorvan Meer, Hans
dc.contributor.authorKubicek, Stefan
dc.contributor.authorLyu, Jeong-ho
dc.contributor.authorCaymax, Matty
dc.contributor.authorLoo, Roger
dc.contributor.authorDe Meyer, Kristin
dc.date.accessioned2021-10-14T11:48:12Z
dc.date.available2021-10-14T11:48:12Z
dc.date.issued1999
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/3936
dc.sourceIIOimport
dc.titleHigh performance raised gate/source/drain transistors for sub-0.15 μm CMOS technologies
dc.typeProceedings paper
dc.contributor.imecauthorKubicek, Stefan
dc.contributor.imecauthorCaymax, Matty
dc.contributor.imecauthorLoo, Roger
dc.contributor.imecauthorDe Meyer, Kristin
dc.contributor.orcidimecLoo, Roger::0000-0003-3513-6058
dc.source.peerreviewno
dc.source.beginpage388
dc.source.endpage391
dc.source.conferenceESSDERC'99 - Proceedings of the 29th European Solid-State Device Research Conference; 13-15 September 1999; Leuven, Belgium.
dc.source.conferencelocation
imec.availabilityPublished - imec


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