iN5 EUV Single Expose Patterning Evaluation for Via Layers

Abstract

The continuous need to shrink dimensions using EUV lithography has posed challenges and opportunities for patterning materials and processes. Scaling BEOL interconnect structured is a key element to performance improvement of functional devices. In this paper, we investigate the impact of various factors on the patterning of EUV single exposure vias, to find effective strategies to shrink critical dimension (CD) with improved critical dimension uniformity (CDU), local critical dimension uniformity (LCDU) and decrease in defectivity. This work is based on patterning a system on chip (SoC) random logic via layer at minimum horizontal interconnect wire pitch of 28nm, which is the limit of single exposure interconnect with 0.33 NA EUV tools. This design uses aggressive CPP/Mx gear ratio of 3/2 which is equivalent to 38nm to 34nm pitch orthogonal via arrays, thus, examining the impact of the primary patterning parameter and illumination source co-optimized with OPC treatment of rectangular vias. The via patterns are transferred to bottom dielectrics to study the evolution of LCDU and defectivity through etch.