Recently added

Cell and module fabrication options for kerfless thin (< 50 μm) epitaxial silicon foils: recent progress and challenges

Sivaramakrishnan Radhakrishnan, Hariharsudan; Cho, Jinyoun; Xu, Menglei; Roth, Julius; Bearda, Twan; Depauw, Valerie; Van Nieuwenhuysen, Kris; Gordon, Ivan; Szlufcik, Jozef; Poortmans, Jef (2018)

Overview of cell fabrication options for thin kerfless epi-Si foils: recent progress and challenges

Sivaramakrishnan Radhakrishnan, Hariharsudan; Cho, Jinyoun; Xu, Menglei; Bearda, Twan; Neubauer, Erich; Kovacova, Zuzana; Kaden, Thomas; Roozeman, R.; Heikkinen, J.; Syvertsen, M.; Ulyashin, A.G.; Röth, Julius; Depauw, Valerie; Van Nieuwenhuysen, Kris; Gordon, Ivan; Szlufcik, Jozef; Poortmans, Jef (2018)

Conference contributions: Recent submissions

Cell and module fabrication options for kerfless thin (< 50 μm) epitaxial silicon foils: recent progress and challenges

Overview of cell fabrication options for thin kerfless epi-Si foils: recent progress and challenges

Deep fingerprinting: undermining website fingerprinting defenses with deep learning

Poster: Knowledge-enriched security and privacy threat modeling

Risk-based design security analysis

Solution-aware data flow diagrams for security threat modelling

Interaction-based privacy threat elicitation

SPARTA: Security & privacy architecture through risk-driven threat assessment

Laser doping from PSG for selective FSF of screen printed rear-junction n-PERT cells

Smart switchable biological surfaces for on-demand biosensing

On the low-frequency noise of high-k gate stacks: what did we learn?

Do we have to worry about extended defects in high-mobility materials?

Impact of defects on transport in nanodevices

Low-frequency noise assessment 0f 1.8 V input-output bulk FinFETs with ALD SiO2

Electrically active defects in plated crystalline silicon n+p solar cells: a DLTS perspective

Metal contamination in semiconductor devices: a never ending story?

ESD diodes with Si/SiGe superlattice I/O finFET architecture in a vertically stacked horizontal nanowire technology

ESD performance comparison of superlattice I/O FinFET and horizontal nanowire devices

Towards efficient and automated side channel evaluations at design time

RGB-NIR demosaicing using deep residual U-net

Conference contributions: Recent submissions

Cell and module fabrication options for kerfless thin (< 50 μm) epitaxial silicon foils: recent progress and challenges ﻿

Overview of cell fabrication options for thin kerfless epi-Si foils: recent progress and challenges ﻿

Deep fingerprinting: undermining website fingerprinting defenses with deep learning ﻿

Poster: Knowledge-enriched security and privacy threat modeling ﻿

Risk-based design security analysis ﻿

Solution-aware data flow diagrams for security threat modelling ﻿

Interaction-based privacy threat elicitation ﻿

SPARTA: Security & privacy architecture through risk-driven threat assessment ﻿

Laser doping from PSG for selective FSF of screen printed rear-junction n-PERT cells ﻿

Smart switchable biological surfaces for on-demand biosensing ﻿

On the low-frequency noise of high-k gate stacks: what did we learn? ﻿

Do we have to worry about extended defects in high-mobility materials? ﻿

Impact of defects on transport in nanodevices ﻿

Low-frequency noise assessment 0f 1.8 V input-output bulk FinFETs with ALD SiO2 ﻿

Electrically active defects in plated crystalline silicon n+p solar cells: a DLTS perspective ﻿

Metal contamination in semiconductor devices: a never ending story? ﻿

ESD diodes with Si/SiGe superlattice I/O finFET architecture in a vertically stacked horizontal nanowire technology ﻿

ESD performance comparison of superlattice I/O FinFET and horizontal nanowire devices ﻿

Towards efficient and automated side channel evaluations at design time ﻿

RGB-NIR demosaicing using deep residual U-net ﻿

Cell and module fabrication options for kerfless thin (< 50 μm) epitaxial silicon foils: recent progress and challenges

Overview of cell fabrication options for thin kerfless epi-Si foils: recent progress and challenges

Deep fingerprinting: undermining website fingerprinting defenses with deep learning

Poster: Knowledge-enriched security and privacy threat modeling

Risk-based design security analysis

Solution-aware data flow diagrams for security threat modelling

Interaction-based privacy threat elicitation

SPARTA: Security & privacy architecture through risk-driven threat assessment

Laser doping from PSG for selective FSF of screen printed rear-junction n-PERT cells

Smart switchable biological surfaces for on-demand biosensing

On the low-frequency noise of high-k gate stacks: what did we learn?

Do we have to worry about extended defects in high-mobility materials?

Impact of defects on transport in nanodevices

Low-frequency noise assessment 0f 1.8 V input-output bulk FinFETs with ALD SiO2

Electrically active defects in plated crystalline silicon n+p solar cells: a DLTS perspective

Metal contamination in semiconductor devices: a never ending story?

ESD diodes with Si/SiGe superlattice I/O finFET architecture in a vertically stacked horizontal nanowire technology

ESD performance comparison of superlattice I/O FinFET and horizontal nanowire devices

Towards efficient and automated side channel evaluations at design time

RGB-NIR demosaicing using deep residual U-net