Publication:

Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node

Date

2021
Proceedings Paper
https://doi.org/10.1109/IEDM19574.2021.9720528
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Author(s)

Chen, Rongmei  
;
Sisto, Giuliano  
;
Jourdain, Anne  
;
Hiblot, Gaspard  
;
Stucchi, Michele  
;
Kakarla, Naveen  
;
Chehab, Bilal  
;
Salahuddin, Shairfe Muhammad  
;
Schleicher, Filip  
;
Veloso, Anabela  
;
Hellings, Geert  
;
Weckx, Pieter  
;
Milojevic, Dragomir  
;
Van der Plas, Geert  
;
Ryckaert, Julien  
;
Beyne, Eric  

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na

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1672 since deposited on 2022-07-09
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Acq. date: 2026-04-06

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