Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node

Abstract

In this work, we explore the resource of backside (BS) interconnect for signal routing in SRAM macro and logic at 2nm technology node to tackle the technology scaling induced frontside (FS) BEOL routing congestion challenge. High-aspect ratio nano-Through-Silicon-Vias (nTSVs) used as BS to FS metal layers connections have been manufactured with sufficiently low resistance (similar to 20 Ohm) and capacitance (similar to 0.04fF). Compared to the FS BEOL, the BS routing is very beneficial in improving delay and power efficiency for long interconnect signal routing. Performance and power efficiency improvement up to 44% and 32% respectively is observed using the BS routing for customized SRAM macros (2nm nanosheet, up to 4Mbit) global routing when compared to the FS counterpart. In addition, the BS routing also leads to logic cells (2nm forksheet, extracted from an ARM (TM) CPU) speed improvement of up to 2.5X and energy efficiency increase of 60% for logic gates driving long interconnect. With capacitance optimization for BS metals, additional 20% performance improvement is observed for SRAM macros and logic cells driving long wirelength.