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Understanding the ISPP Slope in Charge Trap Flash Memory and its Impact on 3-D NAND Scaling

dc.contributor.authorVerreck, Devin
dc.contributor.authorArreghini, Antonio
dc.contributor.authorSchanovsky, F.
dc.contributor.authorRzepa, G.
dc.contributor.authorStanojevic, Z.
dc.contributor.authorMitterbauer, F.
dc.contributor.authorKernstock, C.
dc.contributor.authorBaumgartner, O.
dc.contributor.authorKarner, M.
dc.contributor.authorVan den Bosch, Geert
dc.contributor.authorRosmeulen, Maarten
dc.date.accessioned2022-08-25T15:10:38Z
dc.date.available2022-07-09T02:27:43Z
dc.date.available2022-08-25T15:10:38Z
dc.date.issued2021
dc.identifier.issn2380-9248
dc.identifier.otherWOS:000812325400012
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/40085.2
dc.sourceWOS
dc.titleUnderstanding the ISPP Slope in Charge Trap Flash Memory and its Impact on 3-D NAND Scaling
dc.typeProceedings paper
dc.contributor.imecauthorVerreck, Devin
dc.contributor.imecauthorArreghini, Antonio
dc.contributor.imecauthorVan den Bosch, Geert
dc.contributor.imecauthorRosmeulen, Maarten
dc.contributor.orcidimecVerreck, Devin::0000-0002-3833-5880
dc.contributor.orcidimecArreghini, Antonio::0000-0002-7493-9681
dc.contributor.orcidimecVan den Bosch, Geert::0000-0001-9971-6954
dc.contributor.orcidimecRosmeulen, Maarten::0000-0002-3663-7439
dc.identifier.doi10.1109/IEDM19574.2021.9720506
dc.identifier.eisbn978-1-6654-2572-8
dc.source.numberofpages4
dc.source.peerreviewyes
dc.source.conferenceIEEE International Electron Devices Meeting (IEDM)
dc.source.conferencedateDEC 11-16, 2021
dc.source.conferencelocationSan Francisco
dc.source.journalna
imec.availabilityPublished - imec


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220.500.12860/40085.2*2022-08-25T15:07:10Zvalidation by library/open access desk
120.500.12860/400852022-07-09T02:27:43Z

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