Novel low thermal budget gate stack solutions for BTI reliability in future Logic Device technologies

Abstract

We discuss low thermal budget gate stack solutions for BTI reliability, compatible with novel stacked device integration schemes (e.g., Sequential 3D) and architectures (e.g., nanosheets, CFETs). Dipole formation at the interface between the SiO2 IL and the high-k dielectric improves the nMOS PBTI reliability and enables effective Work Function tuning with a single gate metal, without any sizable impact on the EOT and physical thickness of the gate stack. For pMOS, low temperature exposure of the SiO2 IL to atomic hydrogen before MOW deposition is shown to largely improve NBTI reliability, outmatching conventional RMG solutions based on high temperature 'reliability : anneals' or high-k first integration.