High-K incorporated in a SiON tunnel layer for 3D NAND programming voltage reduction

Abstract

In this paper, we develop a SiON layer with High-K incorporated (HKSiON) for tunnel oxide in a 3D-NAND gate stack. The objective is to improve the programming efficiency that tends to degrade with Z-pitch scaling, as well as with a possible transition from Gate All Around to Trench cells architecture. The results show that increasing the High-K content in a SiON tunnel layer leads to a significant reduction in programming voltage at the expense of retention, therefore causing a trade-off between these two parameters. Low High-K content however, can bring a distinct improvement in programming with limited retention penalty only.