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High-K incorporated in a SiON tunnel layer for 3D NAND programming voltage reduction
dc.contributor.author | Breuil, L. | |
dc.contributor.author | Nyns, L. | |
dc.contributor.author | Rachidi, S. | |
dc.contributor.author | Banerjee, K. | |
dc.contributor.author | Arreghini, A. | |
dc.contributor.author | Bastos, J. | |
dc.contributor.author | Ramesh, S. | |
dc.contributor.author | Van den Bosch, G. | |
dc.contributor.author | Rosmeulen, M. | |
dc.date.accessioned | 2022-10-30T02:54:59Z | |
dc.date.available | 2022-10-30T02:54:59Z | |
dc.date.issued | 2022 | |
dc.identifier.issn | 2330-7978 | |
dc.identifier.other | WOS:000869001800037 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/40642 | |
dc.source | WOS | |
dc.title | High-K incorporated in a SiON tunnel layer for 3D NAND programming voltage reduction | |
dc.type | Proceedings paper | |
dc.contributor.imecauthor | Breuil, L. | |
dc.contributor.imecauthor | Nyns, L. | |
dc.contributor.imecauthor | Rachidi, S. | |
dc.contributor.imecauthor | Banerjee, K. | |
dc.contributor.imecauthor | Arreghini, A. | |
dc.contributor.imecauthor | Bastos, J. | |
dc.contributor.imecauthor | Ramesh, S. | |
dc.contributor.imecauthor | Van den Bosch, G. | |
dc.contributor.imecauthor | Rosmeulen, M. | |
dc.identifier.doi | 10.1109/IMW52921.2022.9779307 | |
dc.identifier.eisbn | 978-1-6654-9947-7 | |
dc.source.numberofpages | 4 | |
dc.source.peerreview | yes | |
dc.source.beginpage | 144 | |
dc.source.endpage | 147 | |
dc.source.conference | 14th IEEE International Memory Workshop (IMW) | |
dc.source.conferencedate | MAR 15-18, 2022 | |
dc.source.conferencelocation | Dresden | |
imec.availability | Under review |
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