Exploring the use of Tungsten-based Hard Masks in BEOL interconnects for 3nm node and beyond

Abstract

Scaling down the average chip size is one of the main drivers in the microelectronics industry, as it broadens the range of applications when smaller, cheaper, more efficient and more powerful chipsets can be installed in tighter packaging. However, scaling down does come with a price, the increased complexity during design and processing. An improvement from the stack composition point of view (materials and thicknesses) is needed, to keep up with the increasing demands while chip downscaling. Novel chip technology nodes require thinner patterning layers, to enable more advanced lithography steps (e.g., EUV lithography), which requires thinner photoresist layers, and therefore, thinner stacks, to transfer the pattern to the dielectric layers underneath [1]. It is in this context when robust and hard to etch materials (Hard Mask materials, HM), with higher etch selectivity are needed. In the Back End Of Line (BEOL), TiN has been used as the HM of choice from many years in dual damascene applications [2]. As we approach to iN3 nodes and beyond, we face several issues while downscaling. The selectivity during dielectric etch may not be high enough to adequately transfer the pattern (line breaks, increased line roughness, loss of self-alignment during via patterning). TiN layer stress may not be suitable for tighter pitches, which may end up causing line wiggling. Another aspect is that fluorine-based chemistries, used to pattern the dielectrics below the HM, may form TiF salts, eventually leading to possible fail mechanisms. Tungsten-containing layers have been proposed as viable candidates to replace TiN as HM in more advanced nodes. In this abstract, we first screen different W-containing layers deposited on blanket wafers, with varying W percentage content. Then, we demonstrate the etch development process of three different W-containing layers, acting as HM in line space patterning at tight pitches: at Metal Pitch 36 nm (MP36, line CD 18 nm), by means of an EUV single print lithography process, and at MP21 (line CD 10.5 nm), realized by means of ArFi lithography process and using a self-aligned quadruple patterning (SAQP) exercise. A first trench etch patterning exercise is done on SAQP P21 line space patterns to extract the average line roughness and HM selectivity values. References [1] D. de Simone et al, High-NA EUVL: the next major step in lithography. https://www.imec-int.com/en/articles/high-na-euvl-next-major-step-lithography [2] H. Shi et al. Plasma processing of low-k dielectrics, chapter 3, ISBN 0470662549