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Modeling and synthesis of timed asynchronous circuits

dc.contributor.authorVanbekbergen, Peter
dc.contributor.authorGoossens, Gert
dc.contributor.authorLin, Bill
dc.date.accessioned2021-09-29T12:50:26Z
dc.date.available2021-09-29T12:50:26Z
dc.date.issued1994
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/408
dc.sourceIIOimport
dc.titleModeling and synthesis of timed asynchronous circuits
dc.typeProceedings paper
dc.contributor.imecauthorVanbekbergen, Peter
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage460
dc.source.endpage465
dc.source.conferenceProceedings European Design Automation Conference (EURODAC) with EURO-VHDL '94
dc.source.conferencedate19/09/1994
dc.source.conferencelocationGrenoble France
imec.availabilityPublished - open access


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