Gate-First High-k/Metal Gate FinFET for advanced DRAM peripheral transistors

Abstract

We report on the patterning of 3D FinFET gates following a gate-first (GF) high-k/metal gate (HKMG) integration. This unconventional GF approach in FinFET fabrication is driven by specific requirements for next generation dynamic random-access memory (DRAM) peripheral transistors. DRAM periphery transistors must be compatible with DRAM process specifications, which implies low cost of ownership and resistance to an extra-long DRAM anneal [1]. With that respect the GF integration was promoted in comparison with the conventional gate last approach used for advanced high-performance logic FinFET devices. Gate-first patterning in this study consists in etching directly a 150 nm n+ poly-Si / 3 nm TiN / 2.2 nm HfO2 / 1.2nm SiO2 gate stack with 45 nm height Si fin topography and at scaled dimensions for the gate (CPP=110nm, Lg=30nm) and fin (pitch=45nm and width= 10nm) as shown in Figure 1. The doped poly Si is meant as a gate electrode, TiN as a work function metal, and HfO2 as a high-k gate dielectric for NMOS and PMOS transistors. The main challenges of the gate etch process are to obtain a straight gate profile and avoid fin attack (breakthrough of HfO2), TiN/HfO2 undercut, within wafer gate CD/Profile non-uniformities and lastly corner residues between gate and fin. While GF HKMG etch has been widely reported for planar logic transistors [2-3], there is a lack of literature regarding the FinFET architecture. In this work, we have investigated different halogen-based plasma chemistries to etch this complex gate stack. Development of the gate etch process has followed two approaches. The first one relies on fluorine-based plasmas to etch the Si/TiN gates selectively to high-k gate dielectric that covers the fins. It has been initially favored thanks to an excellent selectivity to HfO2. However, severe limitations in terms of litho-etch bias and gate CD/profile control can be observed due to micro loading (Figure 2). Increasing gate CD at litho was tried as an alternative to compensate gate CD losses but sidewall roughness, strong bottom gate tapering and TiN undercut remain problematic. To overcome these difficulties, a second approach was proposed using the combination of two etch chemistries: fluorine-based plasma for the doped Si main etch (ME) and bromine-based plasmas for the soft-landing (SL) and over-etch (OE) steps of the gate patterning. A SL process based on HBr/O2/Cl2 chemistry, and a bias pulsing plasma was demonstrated without fin attack and descent gate profile thanks to an optimized selectivity to HfO2 and a more robust passivation layer on the sidewalls of the gate (Figure.3). Improvement of the hard mask open (HMO) and ME steps is also reported in terms of critical dimension (CD) control, within wafer CD uniformity, etch depth uniformity, selectivity, and profile. Last, an isotropic HfO2 etch based on a BCl3/Cl2 cyclic process was demonstrated without fin recess and residues (figure2). We show that a wet clean is needed before the HK etch to remove poly-Si/TiN etch by-products generated by HBr/O2/Cl2 based plasma. [1] A. Spessot et al., Phys. Status Solidi A, vol. 213, no. 2, pp. 245–254, Feb. 2016. [2] A. Le Gouil et al., Journal of Vacuum Science & Technology B 25, 767 (2007). [3] O. Luere et al. Journal of Vacuum Science & Technology B 29, 011024 (2011).