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Impact of Sub-mu m Wafer Thinning on Latch-up Risk in STCO Scaling Era

dc.contributor.authorSerbulova, Kateryna
dc.contributor.authorChen, Shih-Hung
dc.contributor.authorHellings, Geert
dc.contributor.authorHiblot, Gaspard
dc.contributor.authorVeloso, Anabela
dc.contributor.authorJourdain, Anne
dc.contributor.authorDe Boeck, Jo
dc.contributor.authorGroeseneken, Guido
dc.contributor.authorHoriguchi, Naoto
dc.date.accessioned2023-08-10T12:21:53Z
dc.date.available2023-06-20T10:34:35Z
dc.date.available2023-07-07T08:16:40Z
dc.date.available2023-08-10T12:21:53Z
dc.date.issued2021
dc.identifier.issn0739-5159
dc.identifier.otherWOS:000786179000027
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/41855.3
dc.sourceWOS
dc.titleImpact of Sub-mu m Wafer Thinning on Latch-up Risk in STCO Scaling Era
dc.typeProceedings paper
dc.contributor.orcidimecHellings, Geert::0000-0002-5376-2119
dc.contributor.orcidimecGroeseneken, Guido::0000-0003-3763-2098
dc.contributor.orcidimecSerbulova, Kateryna::0000-0001-7326-9949
dc.contributor.orcidimecChen, Shih-Hung::0000-0002-6481-2951
dc.contributor.orcidimecHiblot, Gaspard::0000-0002-3869-965X
dc.contributor.orcidimecDe Boeck, Jo::0000-0001-8244-1552
dc.contributor.orcidimecHoriguchi, Naoto::0000-0001-5490-0416
dc.identifier.doi10.23919/EOS/ESD52038.2021.9574787
dc.identifier.eisbn978-1-58537-329-1
dc.source.numberofpages6
dc.source.peerreviewyes
dc.source.conference43rd Annual EOS/ESD Symposium (EOS/ESD)
dc.source.conferencedateSEP 26-OCT 01, 2021
dc.source.conferencelocationTucson
dc.source.journal43rd Annual EOS/ESD Symposium (EOS/ESD) Proceedings
imec.availabilityPublished - imec


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320.500.12860/41855.3*2023-08-10T12:21:15Zvalidation by library/open access desk
220.500.12860/41855.22023-07-07T08:12:40Zvalidation by imec author
120.500.12860/418552023-06-20T10:34:35Z

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