Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages

Abstract

Chiplet-based multi-die packages implement large numbers of inter-die interconnect bundles clustered in large micro-bump islands. These micro-bumps can be subject to manufacturing defects. The most common defect types are shorts and opens. Traditional interconnect automatic test pattern generation (I-ATPG) algorithms detect, for a given collection of interconnects, all shorts between any pair of interconnects, all open interconnects, and exclude any aliasing, independent from the interconnects' layout positions. Exploiting knowledge of their relative layout positions, we derive a new, improved I-ATPG algorithm. For a user-defined and scalable definition of realistic shorts, the new I-ATPG approach (1) increases the defect coverage significantly (in an example case, between 18% and 67%) by including realistic inter-bundle shorts between micro-bumps from adjacent bundles, and (2) reduces the overall test pattern count (and hence, the resulting test time) by 33% by providing test patterns for realistic shorts only.