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dc.contributor.authorSubhechha, Subhali
dc.contributor.authorCosemans, Stefan
dc.contributor.authorBelmonte, Attilio
dc.contributor.authorRassoul, Nouredine
dc.contributor.authorSharifi, Shamin Houshmand
dc.contributor.authorDebacker, Peter
dc.contributor.authorVerkest, Diederik
dc.contributor.authorDelhougne, Romain
dc.contributor.authorKar, Gouri Sankar
dc.date.accessioned2023-08-02T11:34:27Z
dc.date.available2023-07-28T17:39:36Z
dc.date.available2023-08-02T11:34:27Z
dc.date.issued2023
dc.identifier.issn2330-7978
dc.identifier.otherWOS:001013930200039
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/42222.2
dc.sourceWOS
dc.titleDemonstration of multilevel multiply accumulate operations for AiMC using engineered a-IGZO transistors-based 2T1C gain cell arrays
dc.typeProceedings paper
dc.contributor.imecauthorSubhechha, Subhali
dc.contributor.imecauthorCosemans, Stefan
dc.contributor.imecauthorBelmonte, Attilio
dc.contributor.imecauthorRassoul, Nouredine
dc.contributor.imecauthorSharifi, Shamin Houshmand
dc.contributor.imecauthorDebacker, Peter
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.imecauthorDelhougne, Romain
dc.contributor.imecauthorKar, Gouri Sankar
dc.contributor.orcidimecSubhechha, Subhali::0000-0002-1960-5136
dc.contributor.orcidimecRassoul, Nouredine::0000-0001-9489-3396
dc.contributor.orcidimecDebacker, Peter::0000-0003-3825-5554
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.identifier.doi10.1109/IMW56887.2023.10145946
dc.identifier.eisbn978-1-6654-7459-7
dc.source.numberofpages4
dc.source.peerreviewyes
dc.subject.disciplineElectrical & electronic engineering
dc.source.beginpage153
dc.source.endpage156
dc.source.conference15th IEEE International Memory Workshop (IMW)
dc.source.conferencedateMAY 21-24, 2023
dc.source.conferencelocationMonterey
dc.source.journal15th IEEE International Memory Workshop (IMW) Conference Proceedings
imec.availabilityUnder review


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