Demonstration of multilevel multiply accumulate operations for AiMC using engineered a-IGZO transistors-based 2T1C gain cell arrays

Abstract

We report on the first demonstration of multilevel multiply accumulation operations in 2TIC cell arrays based on amorphous IGZO TFTs for efficient analog in memory compute (AiMC) implementation. Device designs for the read and write transistors to meet the target specifications arc discussed and implemented. Multilevel operations are realized thanks to the long retention time enabled by the ultra-low off-current (<1.5x 10(-19) A/mu m) of the a-IGZO TFTs.