Browsing by author "Rassoul, Nouredine"

Now showing items 1-20 of 48

    • 3D sequential stacked planar devices featuring low-temperature replacement metal gate junctionless top devices with improved reliability 

      Vandooren, Anne; Franco, Jacopo; Parvais, Bertrand; Wu, Zhicheng; Witters, Liesbeth; Walke, Amey; Li, Waikin; Peng, Lan; Deshpande, Veeresh Vidyadhar; Bufler, Fabian; Rassoul, Nouredine; Hellings, Geert; Jamieson, Geraldine; Inoue, Fumihiro; Verbinnen, Greet; Devriendt, Katia; Teugels, Lieve; Heylen, Nancy; Vecchio, Emma; Tao, Zheng; Rosseel, Erik; Vanherle, Wendy; Hikavyy, Andriy; Chan, BT; Ritzenthaler, Romain; Besnard, Guillaume; Schwarzenbach, Walter; Gaudin, Gweltaz; Radu, Ionut; Nguyen, Bich-Yen; Waldron, Niamh; De Heyn, Vincent; Mocuta, Dan; Collaert, Nadine (2018-11)

    • 3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability 

      Vandooren, Anne; Franco, Jacopo; Parvais, Bertrand; Wu, Zhicheng; Witters, Liesbeth; Walke, Amey; Li, Waikin; Peng, Lan; Deshpande, Veeresh Vidyadhar; Bufler, Fabian; Rassoul, Nouredine; Hellings, Geert; Jamieson, Geraldine; Inoue, Fumihiro; Verbinnen, Greet; Devriendt, Katia; Teugels, Lieve; Heylen, Nancy; Vecchio, Emma; Tao, Zheng; Rosseel, Erik; Vanherle, Wendy; Hikavyy, Andriy; Chan, BT; Ritzenthaler, Romain; Besnard, Guillaume; Schwarzenbach, Walter; Gaudin, Gweltaz; Radu, Ionut; Nguyen, Bich-Yen; Waldron, Niamh; De Heyn, Vincent; Mocuta, Dan; Collaert, Nadine (2018)

    • Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications 

      Vandooren, Anne; Wu, Zhicheng; Khaled, Ahmad; Franco, Jacopo; Parvais, Bertrand; Li, W.; Witters, Liesbeth; Walke, Amey; Peng, Lan; Rassoul, Nouredine; Matagne, Philippe; Jamieson, Geraldine; Inoue, Fumihiro; Nguyen, B.Y.; Debruyn, Haroen; Devriendt, Katia; Teugels, Lieve; Heylen, Nancy; Vecchio, Emma; Zheng, T.; Radisic, Dunja; Rosseel, Erik; Vanherle, Wendy; Hikavyy, Andriy; Chan, BT; Besnard, G.; Schwarzenbach, W.; Gaudin, G.; Radu, Iuliana; Waldron, Niamh; De Heyn, Vincent; Demuynck, Steven; Boemmels, Juergen; Ryckaert, Julien; Collaert, Nadine; Mocuta, Dan (2019)

    • Buried Power Rail Integration for CMOS Scaling beyond the 3 nm Node 

      Gupta, Anshul; Tao, Zheng; Radisic, Dunja; Mertens, Hans; Varela Pedreira, Olalla; Demuynck, Steven; Boemmels, Juergen; Devriendt, Katia; Heylen, Nancy; Wang, Shouhua; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Subramanian, Sujith; Schleicher, Filip; Peter, Antony; Rassoul, Nouredine; Siew, Yong Kong; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; Capogreco, Elena; Mannaert, Geert; Sepulveda Marquez, Alfonso; Dupuy, Emmanuel; Vandersmissen, Kevin; Chehab, Bilal; Murdoch, Gayle; Altamirano Sanchez, Efrain; Biesemans, Serge; Tokei, Zsolt; Dentoni Litta, Eugenio; Horiguchi, Naoto (2022)

    • Buried power rail integration with FinFETs for ultimate CMOS scaling 

      Gupta, Anshul; Varela Pedreira, Olalla; Arutchelvan, Goutham; Zahedmanesh, Houman; Devriendt, Katia; Hanssen, Frederik; Tao, Zheng; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Dentoni Litta, Eugenio; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, Noemie; Sepulveda Marquez, Alfonso; Mertens, Sofie; Kim, Min-Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Cousserier, Joris; Yakimets, Dmitry; Lazzarino, Frederic; Chehab, Bilal; Favia, Paola; Drijbooms, Chris; Jaysankar, Manoj; Morin, Pierre; Altamirano Sanchez, Efrain; Mitard, Jerome; Wilson, Chris; Holsteyns, Frank; Boemmels, Juergen; Demuynck, Steven; Tokei, Zsolt; Horiguchi, Naoto (2020)

    • Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node 

      Gupta, Anshul; Mertens, Hans; Tao, Zheng; Demuynck, Steven; Boemmels, Juergen; Arutchelvan, Goutham; Devriendt, Katia; Varela Pedreira, Olalla; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Zahedmanesh, Houman; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Dentoni Litta, Eugenio; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, N.; Sepulveda Marquez, Alfonso; Mertens, Sofie; Kim, Min Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Yakimets, Dmitry; Chehab, Bilal; Favia, Paola; Drijbooms, Chris; Cousserier, Joris; Jaysankar, Manoj; Lazzarino, Frederic; Morin, Pierre; Altamirano Sanchez, Efrain; Mitard, Jerome; Wilson, Chris; Holsteyns, Frank; Tokei, Zsolt; Horiguchi, Naoto (2020)

    • Capacitor-less, Long-Retention (> 400s) DRAM Cell Paving the Way towards Low-Power and High-Density Monolithic 3D DRAM 

      Belmonte, Attilio; Oh, Hyungrock; Rassoul, Nouredine; Donadio, Gabriele Luca; Mitard, Jerome; Dekkers, Harold; Delhougne, Romain; Subhechha, Subhali; Vaisman Chasin, Adrian; van Setten, Michiel; Kljucar, Luka; Mao, Ming; Puliyalil, Harinarayanan; Pak, Murat; Teugels, Lieve; Tsvetanova, Diana; Banerjee, Kaustuv; Souriau, Laurent; Tokei, Zsolt; Goux, Ludovic; Kar, Gouri Sankar (2020)

    • Characterization of optical end-point detection for via reveal processing 

      Rassoul, Nouredine; Jourdain, Anne; Tutunjyan, Nina; De Vos, Joeri; Sardo, Stefano; Piumi, Daniele; Miller, Andy; Beyne, Eric; Walsby, Edward; Ashraf, Huma; Thomas, Dave (2018)

    • Characterizing and Modelling of the BTI Reliability in IGZO-TFT using Light-assisted I-V Spectroscopy 

      Wu, Zhicheng; Vaisman Chasin, Adrian; Franco, Jacopo; Subhechha, Subhali; Dekkers, Harold; Yengula Venkata Ramana, Bhuvaneshwari; Belmonte, Attilio; Rassoul, Nouredine; van Setten, Michiel; Afanas'ev, V.; Delhougne, Romain; Kaczer, Ben; Kar, Gouri Sankar (2022)

    • Degradation Mapping and Impact of Device Dimension on IGZO TFTs BTI 

      Rinaudo, Pietro; Vaisman Chasin, Adrian; Franco, Jacopo; Wu, Zhicheng; Subhechha, Subhali; Arutchelvan, Goutham; Eneman, Geert; Yengula Venkata Ramana, Bhuvaneshwari; Rassoul, Nouredine; Delhougne, Romain; Kaczer, Ben; De Wolf, Ingrid; Kar, Gouri Sankar (2023)

    • Degradation mapping of IGZO TFTs 

      Rinaudo, P.; Vaisman Chasin, Adrian; Franco, Jacopo; Wu, Zhicheng; Rassoul, Nouredine; Delhougne, Romain; Kaczer, Ben; De Wolf, Ingrid; Kar, Gouri Sankar (2022)

    • Demonstration of multilevel multiply accumulate operations for AiMC using engineered a-IGZO transistors-based 2T1C gain cell arrays 

      Subhechha, Subhali; Cosemans, Stefan; Belmonte, Attilio; Rassoul, Nouredine; Houshmand Sharifi, Shamin; Debacker, Peter; Verkest, Diederik; Delhougne, Romain; Kar, Gouri Sankar (2023)

    • Deposition, Characterization, and Performance of Spinel InGaZnO4 

      Dekkers, Harold; van Setten, Michiel; Belmonte, Attilio; Vaisman Chasin, Adrian; Subhechha, Subhali; Rassoul, Nouredine; Glushkova, Anastasia; Delhougne, Romain; Kar, Gouri Sankar (2022-02-23)

    • Device engineering guidelines for performance boost in IGZO front gated TFTs based on defect control 

      Subhechha, Subhali; Rassoul, Nouredine; Belmonte, Attilio; Hody, Hubert; Dekkers, Harold; van Setten, Michiel; Vaisman Chasin, Adrian; Houshmand Sharifi, Shamin; Banerjee, Kaustuv; Puliyalil, Harinarayanan; Kundu, Souvik; Pak, Murat; Tsvetanova, Diana; Bazzazian, Nina; Vandersmissen, Kevin; Batuk, Dmitry; Geypen, Jef; Heijlen, Jeroen; Delhougne, Romain; Kar, Gouri Sankar (2022)

    • Device modeling of two-steps oxygen anneal-based submicron InGaZnO back-end-of-line field-effect transistor enabling short-channel effects suppression 

      Kim, Donguk; Kim, Je-Hyuk; Choi, Woo Sik; Yang, Tae Jun; Jang, Jun Tae; Belmonte, Attilio; Rassoul, Nouredine; Subhechha, Subhali; Delhougne, Romain; Kar, Gouri Sankar; Lee, Wonsok; Cho, Min Hee; Ha, Daewon; Kim, Dae Hwan (2022)

    • Direct metal etch evaluation for advanced interconnect 

      Paolillo, Sara; Lazzarino, Frederic; Rassoul, Nouredine; Wan, Danny; Piumi, Daniele; Tokei, Zsolt (2017)

    • Direct metal etch for advanced interconnect 

      Paolillo, Sara; Wan, Danny; Lazzarino, Frederic; Rassoul, Nouredine; Piumi, Daniele; Tokei, Zsolt (2018)

    • Enhanced data integrity of In-Ga-Zn-Oxide based Capacitor-less 2T memory for DRAM applications 

      Oh, Hyungrock; Belmonte, Attilio; Perumkunnil, Manu; Mitard, Jerome; Rassoul, Nouredine; Donadio, Gabriele Luca; Delhougne, Romain; Furnemont, Arnaud; Kar, Gouri Sankar; Dehaene, Wim (2021)

    • Etch process modules development and integration in 3D SOC applications 

      Tutunjyan, Nina; Sardo, Stefano; De Vos, Joeri; Van Huylenbroeck, Stefaan; Jourdain, Anne; Peng, Lan; Inoue, Fumihiro; Rassoul, Nouredine; Beyer, Gerald; Beyne, Eric; Miller, Andy; Piumi, Daniele; Walsby, Edward; Ansell, Oliver; Ashraf, Huma; Thomas, Dave (2017)

    • Etch process modules development and integration in 3D-SOC applications 

      Tutunjyan, Nina; Sardo, Stefano; De Vos, Joeri; Van Huylenbroeck, Stefaan; Jourdain, Anne; Peng, Lan; Inoue, Fumihiro; Rassoul, Nouredine; Beyer, Gerald; Beyne, Eric; Miller, Andy; Piumi, Daniele (2018)