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Buried Power Rail Integration for CMOS Scaling beyond the 3 nm Node
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Authors
Gupta, Anshul
;
Tao, Zheng
;
Radisic, Dunja
;
Mertens, Hans
;
Varela Pedreira, Olalla
;
Demuynck, Steven
;
Boemmels, Juergen
;
Devriendt, Katia
;
Heylen, Nancy
;
Wang, Shouhua
;
Kenis, Karine
;
Teugels, Lieve
;
Sebaai, Farid
;
Lorant, Christophe
;
Jourdan, Nicolas
;
Chan, BT
;
Subramanian, Sujith
;
Schleicher, Filip
;
Peter, Antony
;
Rassoul, Nouredine
;
Siew, Yong Kong
;
Briggs, Basoene
;
Zhou, Daisy
;
Rosseel, Erik
;
Capogreco, Elena
;
Mannaert, Geert
;
Sepulveda Marquez, Alfonso
;
Dupuy, Emmanuel
;
Vandersmissen, Kevin
;
Chehab, Bilal
;
Murdoch, Gayle
;
Altamirano Sanchez, Efrain
;
Biesemans, Serge
;
Tokei, Zsolt
;
Dentoni Litta, Eugenio
;
Horiguchi, Naoto
DOI
10.1117/12.2615641
EISBN
978-1-5106-4988-0
ISBN
978-1-5106-4987-3
ISSN
0277-786X
Conference
Conference on Advanced Etch Technology and Process Integration for Nanopatterning XI Part of SPIE Advanced Lithography and Patterning Conference
Journal
Proceedings of SPIE
Volume
12056
Title
Buried Power Rail Integration for CMOS Scaling beyond the 3 nm Node
Publication type
Proceedings paper
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Conference contributions
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Version
Item
Date
Summary
2
20.500.12860/40366.2
*
2023-04-26T08:28:26Z
validation by library/open access desk
1
20.500.12860/40366
2022-09-08T02:38:37Z
*Selected version
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