Browsing by author "Mannaert, Geert"
Now showing items 1-20 of 87
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3D sequential CMOS top tier devices demonstration using a low temperature Smart Cu (TM) Si layer transfer
Besnard, Guillaume; Radu, Ionut; Vandooren, Anne; Wu, Zhicheng; Franco, Jacopo; Li, Waikin; Arimura, Hiroaki; Mannaert, Geert; Rosseel, Erik; Hikavyy, Andriy; Dentoni Litta, Eugenio; Horiguchi, Naoto (2021) -
3D sequential low temperature top tier devices using dopant activation with excimer laser anneal and strained silicon as performance boosters
Vandooren, Anne; Wu, Zhicheng; Parihar, Narendra; Franco, Jacopo; Parvais, Bertrand; Matagne, Philippe; Debruyn, Haroen; Mannaert, Geert; Devriendt, Katia; Teugels, Lieve; Vecchio, Emma; Radisic, Dunja; Rosseel, Erik; Hikavyy, Andriy; Chan, BT; Waldron, Niamh; Mitard, Jerome; Besnard, G.; Alvarez, A.; Gaudin, G.; Schwarzenbach, W.; Radu, I.; Nguyen, B. Y.; Huet, K.; Tabata, T.; Mazzamuto, F.; Demuynck, Steven; Boemmels, Juergen; Collaert, Nadine; Horiguchi, Naoto (2020) -
A low cost 90nm RF-CMOS platform for record RF circuit performance
Jeamsaksiri, Wutthinan; Linten, Dimitri; Thijs, Steven; Carchon, Geert; Ramos, Javier; Mercha, Abdelkarim; Sun, Xiao; Soussan, Philippe; Dehan, Morin; Chiarella, Thomas; Venegas, Rafael; Subramanian, Vaidy; Scholten, A.; Wambacq, Piet; Velghe, Rudolf; Mannaert, Geert; Heylen, Nancy; Verbeeck, Rita; Boullart, Werner; Heyvaert, Ilse; Mahadeva Iyer, Natarajan; Groeseneken, Guido; Debusschere, Ingrid; Biesemans, Serge; Decoutere, Stefaan (2005-06) -
Advanced transistors for high frequency applications
Parvais, Bertrand; Peralagu, Uthayasankaran; Alian, AliReza; Vais, Abhitosh; Witters, Liesbeth; Mols, Yves; Walke, Amey; Ingels, Mark; Yu, Hao; Putcha, Vamsi; Khaled, Ahmad; Rodriguez, Raul; Sibaja-Hernandez, Arturo; Yadav, Sachin; ElKashlan, Rana Y.; Baryshnikova, Marina; Mannaert, Geert; Alcotte, Reynald; Simoen, Eddy; Zhao, Ming; zhao, ellen; De Jaeger, Brice; Fleetwood, D.M.; Langer, Robert; Wambacq, Piet; Kunert, Bernardette; Waldron, Niamh; Collaert, Nadine (2020) -
Advanced wafer surface cleaning technology
Mertens, Paul; Vos, Rita; Vereecke, Guy; Arnauts, Sophia; Bearda, Twan; De Waele, Rita; Eitoku, Atsuro; Fyen, Wim; Geckiere, J.; Hellin, David; Holsteyns, Frank; Kesters, Els; Claes, Martine; Kenis, Karine; Kraus, Harald; Malhouitre, Stephane; Lee, Kuntack; Kocsis, Michael; Onsia, Bart; Garaud, Sylvain; Rip, Jens; Snow, Jim; Teerlinck, I.; Van Hoeymissen, Jan; Barbagini, Francesca; Xu, Kaidong; Paraschiv, Vasile; De Gendt, Stefan; Mannaert, Geert; Heyns, Marc (2004) -
Au-free AlGaN/GaN power diode on 8 in Si substrate with gated edge termination
Lenci, Silvia; De Jaeger, Brice; Carbonell, Laure; Hu, Jie; Mannaert, Geert; Wellekens, Dirk; You, Shuzhen; Bakeroot, Benoit; Decoutere, Stefaan (2013) -
Au-free CMOS-compatible AlGaN/GaN HEMT processing on 200 mm Si substrates
De Jaeger, Brice; Van Hove, Marleen; Wellekens, Dirk; Kang, Xuanwu; Liang, Hu; Mannaert, Geert; Geens, Karen; Decoutere, Stefaan (2012) -
Buried Power Rail Integration for CMOS Scaling beyond the 3 nm Node
Gupta, Anshul; Tao, Zheng; Radisic, Dunja; Mertens, Hans; Varela Pedreira, Olalla; Demuynck, Steven; Boemmels, Juergen; Devriendt, Katia; Heylen, Nancy; Wang, Shouhua; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Subramanian, Sujith; Schleicher, Filip; Peter, Antony; Rassoul, Nouredine; Siew, Yong Kong; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; Capogreco, Elena; Mannaert, Geert; Sepulveda Marquez, Alfonso; Dupuy, Emmanuel; Vandersmissen, Kevin; Chehab, Bilal; Murdoch, Gayle; Altamirano Sanchez, Efrain; Biesemans, Serge; Tokei, Zsolt; Dentoni Litta, Eugenio; Horiguchi, Naoto (2022) -
Buried power rail integration with FinFETs for ultimate CMOS scaling
Gupta, Anshul; Varela Pedreira, Olalla; Arutchelvan, Goutham; Zahedmanesh, Houman; Devriendt, Katia; Hanssen, Frederik; Tao, Zheng; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Dentoni Litta, Eugenio; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, Noemie; Sepulveda Marquez, Alfonso; Mertens, Sofie; Kim, Min-Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Cousserier, Joris; Yakimets, Dmitry; Lazzarino, Frederic; Chehab, Bilal; Favia, Paola; Drijbooms, Chris; Jaysankar, Manoj; Morin, Pierre; Altamirano Sanchez, Efrain; Mitard, Jerome; Wilson, Chris; Holsteyns, Frank; Boemmels, Juergen; Demuynck, Steven; Tokei, Zsolt; Horiguchi, Naoto (2020) -
Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node
Gupta, Anshul; Mertens, Hans; Tao, Zheng; Demuynck, Steven; Boemmels, Juergen; Arutchelvan, Goutham; Devriendt, Katia; Varela Pedreira, Olalla; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Zahedmanesh, Houman; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Dentoni Litta, Eugenio; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, N.; Sepulveda Marquez, Alfonso; Mertens, Sofie; Kim, Min Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Yakimets, Dmitry; Chehab, Bilal; Favia, Paola; Drijbooms, Chris; Cousserier, Joris; Jaysankar, Manoj; Lazzarino, Frederic; Morin, Pierre; Altamirano Sanchez, Efrain; Mitard, Jerome; Wilson, Chris; Holsteyns, Frank; Tokei, Zsolt; Horiguchi, Naoto (2020) -
Characterization of epitaxial Si:C:P and SI:P layers for source/drain formation in advanced bulk FinFETs
Rosseel, Erik; Profijt, Harald; Hikavyy, Andriy; Tolle, John; Kubicek, Stefan; Mannaert, Geert; L'abbe, Caroline; Wostyn, Kurt; Horiguchi, Naoto; Clarysse, Trudo; Parmentier, Brigitte; Dhayalan, Sathish Kumar; Bender, Hugo; Maes, Jan; Mehta, Sandeep; Loo, Roger (2014-10) -
Characterization of epitaxial Si:C:P and Si:P layers for source/drain formation in advanced bulk finFETs
Rosseel, Erik; Profijt, Harald; Hikavyy, Andriy; Tolle, John; Kubicek, Stefan; Mannaert, Geert; L'abbe, Caroline; Wostyn, Kurt; Horiguchi, Naoto; Clarysse, Trudo; Parmentier, Brigitte; Dhayalan, Sathish Kumar; Bender, Hugo; Maes, Jan Willem; Loo, Roger (2014-10) -
CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits
Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O'Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto (2018) -
CMOS integration of thermally stable diffusion and gate replacement (D&GR) high-k/metal gate stacks in DRAM periphery transistors
Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O'Sullivan, Barry; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto (2017) -
CMOS patterning over high aspect ratio topographies for N10/N7 using spin-on carbon hardmasks
Hopf, Toby; Ercken, Monique; Mannaert, Geert; Kunnen, Eddy; Tao, Zheng; Vandenbroeck, Nadia; Sebaai, Farid; Kikuchi, Yoshiaki; Mertens, Hans; Kubicek, Stefan; Demuynck, Steven; Horiguchi, Naoto (2017) -
CMOS patterning over high-aspect ratio topographies for N10/N7 using spin-on carbon hardmasks
Hopf, Toby; Ercken, Monique; Mannaert, Geert; Kunnen, Eddy; Tao, Zheng; Vandenbroeck, Nadia; Sebaai, Farid; Kikuchi, Yoshiaki; Mertens, Hans; Kubicek, Stefan; Demuynck, Steven; Horiguchi, Naoto (2017) -
CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach
Kottantharayil, Anil; Verheyen, Peter; Collaert, Nadine; Dixit, Abhisek; Kaczer, Ben; Snow, Jim; Vos, Rita; Locorotondo, Sabrina; Degroote, Bart; Shi, Xiaoping; Rooyackers, Rita; Mannaert, Geert; Brus, Stephan; Yim, Yong Sik; Lauwers, Anne; Goodwin, Michael; Kittl, Jorge; Van Dal, Mark; Richard, Olivier; Veloso, Anabela; Kubicek, Stefan; Beckx, Stephan; Boullart, Werner; De Meyer, Kristin; Absil, Philippe; Jurczak, Gosia; Biesemans, Serge (2005) -
Comparison of Electrical Performance of Co-Integrated Forksheets and Nanosheets Transistors for the 2nm Technological Node and Beyond
Ritzenthaler, Romain; Mertens, Hans; Eneman, Geert; Simoen, Eddy; Bury, Erik; Eyben, Pierre; Bufler, Fabian; Oniki, Yusuke; Briggs, Basoene; Chan, BT; Hikavyy, Andriy; Mannaert, Geert; Parvais, Bertrand; Vaisman Chasin, Adrian; Mitard, Jerome; Dentoni Litta, Eugenio; Samavedam, Sri; Horiguchi, Naoto (2021) -
Cumulated charging mechanisms at gate processing in high-kappa first planar NMOS devices
Hiblot, Gaspard; Parihar, Narendra; Dupuy, Emmanuel; Mannaert, Geert; Baudot, Sylvain; Kaczer, Ben; De Heyn, Vincent; Mercha, Abdelkarim (2020) -
Defect mitigation in sub-20 nm patterning with high-chi, silicon containing block copolymers
Doise, Jan; Mannaert, Geert; Suh, Hyo Seon; Rincon Delgadillo, Paulina; Vandenberghe, Geert; Willson, C. Grant; Ellison, Christopher J. (2018)