Browsing by author "Lorant, Christophe"

Now showing items 1-20 of 26

    • 12-EUV layer Surrounding Gate Transistor (SGT) for vertical 6-T SRAM: 5-nm-class technology for ultra-density logic devices 

      Kim, Min-Soo; Harada, N.; Kikuchi, Yoshiaki; Boemmels, Juergen; Mitard, Jerome; Huynh Bao, Trong; Matagne, Philippe; Tao, Zheng; Li, Waikin; Devriendt, Katia; Ragnarsson, Lars-Ake; Lorant, Christophe; Sebaai, Farid; Porret, Clément; Rosseel, Erik; Dangol, Anish; Batuk, Dmitry; Martinez Alanis, Gerardo Tadeo; Geypen, Jef; Jourdan, Nicolas; Sepulveda Marquez, Alfonso; Puliyalil, Harinarayanan; Jamieson, Geraldine; van der Veen, Marleen; Teugels, Lieve; El-Mekki, Zaid; Altamirano Sanchez, Efrain; Li, Y.; Nakamura, H.; Mocuta, Dan; Matsuoka, F. (2019)

    • 21 nm Pitch dual-damascene BEOL process integration with full barrierless Ru metallization 

      Vega Gonzalez, Victor; Wilson, Chris; Paolillo, Sara; Decoster, Stefan; Mao, Ming; Versluijs, Janko; Blanco, Victor; Kesters, Els; Le, Quoc Toan; Lorant, Christophe; Varela Pedreira, Olalla; Lesniewska, Alicja; Heylen, Nancy; El-Mekki, Zaid; van der Veen, Marleen; Webers, Tomas; Vats, Hemant; Rynders, Luc; Cupak, Miroslav; Lee, Jae Uk; Drissi, Youssef; Halipre, Luc; Charley, Anne-Laure; Verdonck, Patrick; Witters, Thomas; Van Gompel, Sander; Kimura, Yosuke; Jourdan, Nicolas; Ciofi, Ivan; Contino, Antonino; Boccardi, Guillaume; Lariviere, Stephane; De Wachter, Bart; Vancoille, Eric; Lazzarino, Frederic; Ercken, Monique; Kim, Ryan Ryoung han; Trivkovic, Darko; Croes, Kristof; Leray, Philippe; Pardons, Katrien; Barla, Kathy; Tokei, Zsolt (2019)

    • A method to pattern tight tip-to-tip in 32nm-pitch N5 interconnect using Ru area selective deposition tone inversion process 

      Briggs, Basoene; Soethoudt, Job; Delabie, Annelies; Wilson, Chris; Tokei, Zsolt; Boemmels, Juergen; Devriendt, Katia; Sebaai, Farid; Lorant, Christophe; Hody, Hubert (2018)

    • Alternative metal recess for fully-self-aligned-vias 

      Contino, Antonino; Le, Quoc Toan; Sakamoto, Kei; Schleicher, Filip; Paolillo, Sara; Pacco, Antoine; Kesters, Els; Lorant, Christophe; Murdoch, Gayle; Lariviere, Stephane; Vega Gonzalez, Victor; Versluijs, Janko; Jaenen, Patrick; Teugels, Lieve; van der Veen, Marleen; Jourdan, Nicolas; Ciofi, Ivan; Boccardi, Guillaume; Tokei, Zsolt; Wilson, Chris (2020)

    • Bare wafer analysis for wet cleaning efficiency – The impact of classification and sensitivity 

      Wendt, Kay; Wilbers, Fabian; Ruth, Jochen; Lorant, Christophe; Holsteyns, Frank; Newby, John; Bast, Gerhard; Sundar, Vignesh (2018)

    • Buried Power Rail Integration for CMOS Scaling beyond the 3 nm Node 

      Gupta, Anshul; Tao, Zheng; Radisic, Dunja; Mertens, Hans; Varela Pedreira, Olalla; Demuynck, Steven; Boemmels, Juergen; Devriendt, Katia; Heylen, Nancy; Wang, Shouhua; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Subramanian, Sujith; Schleicher, Filip; Peter, Antony; Rassoul, Nouredine; Siew, Yong Kong; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; Capogreco, Elena; Mannaert, Geert; Sepulveda Marquez, Alfonso; Dupuy, Emmanuel; Vandersmissen, Kevin; Chehab, Bilal; Murdoch, Gayle; Altamirano Sanchez, Efrain; Biesemans, Serge; Tokei, Zsolt; Dentoni Litta, Eugenio; Horiguchi, Naoto (2022)

    • Buried power rail integration with FinFETs for ultimate CMOS scaling 

      Gupta, Anshul; Varela Pedreira, Olalla; Arutchelvan, Goutham; Zahedmanesh, Houman; Devriendt, Katia; Hanssen, Frederik; Tao, Zheng; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Dentoni Litta, Eugenio; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, Noemie; Sepulveda Marquez, Alfonso; Mertens, Sofie; Kim, Min-Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Cousserier, Joris; Yakimets, Dmitry; Lazzarino, Frederic; Chehab, Bilal; Favia, Paola; Drijbooms, Chris; Jaysankar, Manoj; Morin, Pierre; Altamirano Sanchez, Efrain; Mitard, Jerome; Wilson, Chris; Holsteyns, Frank; Boemmels, Juergen; Demuynck, Steven; Tokei, Zsolt; Horiguchi, Naoto (2020)

    • Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node 

      Gupta, Anshul; Mertens, Hans; Tao, Zheng; Demuynck, Steven; Boemmels, Juergen; Arutchelvan, Goutham; Devriendt, Katia; Varela Pedreira, Olalla; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Zahedmanesh, Houman; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Dentoni Litta, Eugenio; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, N.; Sepulveda Marquez, Alfonso; Mertens, Sofie; Kim, Min Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Yakimets, Dmitry; Chehab, Bilal; Favia, Paola; Drijbooms, Chris; Cousserier, Joris; Jaysankar, Manoj; Lazzarino, Frederic; Morin, Pierre; Altamirano Sanchez, Efrain; Mitard, Jerome; Wilson, Chris; Holsteyns, Frank; Tokei, Zsolt; Horiguchi, Naoto (2020)

    • Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond 

      Gupta, Anshul; Varela Pedreira, Olalla; Tao, Zheng; Mertens, Hans; Radisic, Dunja; Jourdan, Nicolas; Devriendt, Katia; Heylen, Nancy; Wang, Shouhua; Chehab, Bilal; Jang, Doyoung; Hellings, Geert; Sebaai, Farid; Lorant, Christophe; Teugels, Lieve; Peter, Antony; Chan, BT; Schleicher, Filip; Demonie, Ingrid; Marien, Philippe; Sepulveda Marquez, Alfonso; Richard, Olivier; Nagesh, Nishanth; Lesniewska, Alicja; Lazzarino, Frederic; Ryckaert, Julien; Morin, Pierre; Altamirano Sanchez, Efrain; Murdoch, Gayle; Boemmels, Juergen; Demuynck, Steven; Na, Myung Hee; Tokei, Zsolt; Biesemans, Serge; Dentoni Litta, Eugenio; Horiguchi, Naoto (2020)

    • Challenges on surface conditioning in 3D device architectures: triple-gate FinFETs, gate-all-around lateral and vertical nanowire FETs 

      Veloso, Anabela; Paraschiv, Vasile; Vecchio, Emma; Devriendt, Katia; Li, Waikin; Simoen, Eddy; Chan, BT; Tao, Zheng; Rosseel, Erik; Loo, Roger; Milenin, Alexey; Kunert, Bernardette; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; van Dorp, Dennis; Altamirano Sanchez, Efrain; Brus, Stephan; Marien, Philippe; Fleischmann, Claudia; Melkonyan, Davit; Huynh Bao, Trong; Eneman, Geert; Hellings, Geert; Sibaja-Hernandez, Arturo; Matagne, Philippe; Waldron, Niamh; Mocuta, Dan; Collaert, Nadine (2017)

    • Challenges on surface conditioning in 3D device architectures: triple-gate finFETs, gate-all-around lateral and vertical nanowireFETs 

      Veloso, Anabela; Paraschiv, Vasile; Vecchio, Emma; Devriendt, Katia; Li, Waikin; Simoen, Eddy; Chan, BT; Tao, Zheng; Rosseel, Erik; Loo, Roger; Milenin, Alexey; Kunert, Bernardette; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; van Dorp, Dennis; Altamirano Sanchez, Efrain; Brus, Stephan; Marien, Philippe; Sibaja-Hernandez, Arturo; Matagne, Philippe; Waldron, Niamh; Mocuta, Dan; Collaert, Nadine (2017)

    • CMOS area scaling and the need for high aspect ratio vias 

      Briggs, Basoene; Guissi, Sofiane; Wilson, Chris; Ryckaert, Julien; Paolillo, Sara; Vandersmissen, Kevin; Versluijs, Janko; Lorant, Christophe; Heylen, Nancy; Boemmels, Juergen; Tokei, Zsolt; Sherazi, Yasser; Weckx, Pieter; Kljucar, Luka; van der Veen, Marleen; Boccardi, Guillaume; De Heyn, Vincent; Gupta, Anshul; Ervin, Joseph; Kamon, Matt (2018)

    • CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits 

      Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O'Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto (2018)

    • CMOS integration of thermally stable diffusion and gate replacement (D&GR) high-k/metal gate stacks in DRAM periphery transistors 

      Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O'Sullivan, Barry; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto (2017)

    • DTCO and TCAD for a 12 layer-EUV ultra-scaled surrounding gate transistor 6T-SRAM 

      Matagne, Philippe; Nakamura, H.; Kim, Min-Soo; Kikuchi, Yoshiaki; Huynh Bao, Trong; Tao, Zheng; Li, Waikin; Devriendt, Katia; Ragnarsson, Lars-Ake; Boemmels, Juergen; Mallik, Arindam; Altamirano Sanchez, Efrain; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Porret, Clément; Mocuta, Dan; Harada, N.; Matsuoka, F. (2018)

    • Exploration of EUV-based self-aligned multipatterning (SAMP) options targeting pitches below 20 nm 

      Decoster, Stefan; Lazzarino, Frederic; Vangoidsenhoven, Diziana; Blanco, Victor; Tamaddon, Amir-Hossein; Kesters, Els; Lorant, Christophe (2019)

    • FEOL patterning challenges in scaled SRAM with vertical Surrounding Gate Transistors (SGT) 

      Tao, Zheng; Li, Waikin; Kim, Min-Soo; Devriendt, Katia; Lorant, Christophe; Sebaai, Farid; Porret, Clément; Rosseel, Erik; Sepulveda Marquez, Alfonso; Jourdan, Nicolas; Kikuchi, Yoshiaki; Boemmels, Juergen; Mitard, Jerome; Matagne, Philippe; Ragnarsson, Lars-Ake; Dangol, Anish; Batuk, Dmitry; Martinez Alanis, Gerardo Tadeo; Geypen, Jef; Altamirano Sanchez, Efrain; Lee, James; Li, YiSuo; Kanazawa, Kenichi; Harada, Nozomu; Masuoka, Fujio (2019)

    • Fin bending in dimensional scaling 

      Zhang, Liping; Hellin, David; Sepulveda Marquez, Alfonso; Altamirano Sanchez, Efrain; Lazzarino, Frederic; Morin, Pierre; Wang, Shouhua; Hopf, Toby; Kenis, Karine; Lorant, Christophe; Sebaai, Farid; Batuk, Dmitry; Briggs, Basoene; Mertens, Hans; Demuynck, Steven (2020)

    • Interconnects for scaled SRAM with vertical Surrounded Gate Transistors (SGT) 

      Boemmels, Juergen; Harada, N.; Kim, Min-Soo; Mitard, Jerome; Kikuchi, Yoshiaki; Li, Waikin; Tao, Zheng; Puliyalil, Harinarayanan; Devriendt, Katia; Lorant, Christophe; Le, Quoc Toan; Kesters, Els; Jourdan, Nicolas; El-Mekki, Zaid; Teugels, Lieve; van der Veen, Marleen; Li, Y.; Nakamura, H.; Mocuta, Dan; Masuoka, F. (2019)

    • One micron redistribution for fan-out wafer level packaging 

      Flack, Warren; Hsieh, Robert; Nguyen, Ha-Ai; Slabbekoorn, John; Lorant, Christophe; Miller, Andy (2017)