Browsing by author "Chehab, Bilal"

A Comprehensive Study of Nanosheet and Forksheet SRAM for Beyond N5 Node

Gupta, Mohit; Weckx, Pieter; Schuddinck, Pieter; Jang, Doyoung; Chehab, Bilal; Cosemans, Stefan; Ryckaert, Julien; Dehaene, Wim (2021)

Application of cell-aware test on an advanced 3nm CMOS technology library

Gao, Zhan; Hu, Min-Chun; Baert, Rogier; Chehab, Bilal; Malagi, Santosh; Swenton, Joe; Huisken, Jos; Goossens, Kees; Marinissen, Erik Jan (2019-11)

Buried Power Rail Integration for CMOS Scaling beyond the 3 nm Node

Gupta, Anshul; Tao, Zheng; Radisic, Dunja; Mertens, Hans; Varela Pedreira, Olalla; Demuynck, Steven; Boemmels, Juergen; Devriendt, Katia; Heylen, Nancy; Wang, Shouhua; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Subramanian, Sujith; Schleicher, Filip; Peter, Antony; Rassoul, Nouredine; Siew, Yong Kong; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; Capogreco, Elena; Mannaert, Geert; Sepulveda Marquez, Alfonso; Dupuy, Emmanuel; Vandersmissen, Kevin; Chehab, Bilal; Murdoch, Gayle; Altamirano Sanchez, Efrain; Biesemans, Serge; Tokei, Zsolt; Dentoni Litta, Eugenio; Horiguchi, Naoto (2022)

Buried power rail integration with FinFETs for ultimate CMOS scaling

Gupta, Anshul; Varela Pedreira, Olalla; Arutchelvan, Goutham; Zahedmanesh, Houman; Devriendt, Katia; Hanssen, Frederik; Tao, Zheng; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Dentoni Litta, Eugenio; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, Noemie; Sepulveda Marquez, Alfonso; Mertens, Sofie; Kim, Min-Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Cousserier, Joris; Yakimets, Dmitry; Lazzarino, Frederic; Chehab, Bilal; Favia, Paola; Drijbooms, Chris; Jaysankar, Manoj; Morin, Pierre; Altamirano Sanchez, Efrain; Mitard, Jerome; Wilson, Chris; Holsteyns, Frank; Boemmels, Juergen; Demuynck, Steven; Tokei, Zsolt; Horiguchi, Naoto (2020)

Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node

Gupta, Anshul; Mertens, Hans; Tao, Zheng; Demuynck, Steven; Boemmels, Juergen; Arutchelvan, Goutham; Devriendt, Katia; Varela Pedreira, Olalla; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Zahedmanesh, Houman; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Dentoni Litta, Eugenio; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, N.; Sepulveda Marquez, Alfonso; Mertens, Sofie; Kim, Min Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Yakimets, Dmitry; Chehab, Bilal; Favia, Paola; Drijbooms, Chris; Cousserier, Joris; Jaysankar, Manoj; Lazzarino, Frederic; Morin, Pierre; Altamirano Sanchez, Efrain; Mitard, Jerome; Wilson, Chris; Holsteyns, Frank; Tokei, Zsolt; Horiguchi, Naoto (2020)

Buried Power Rail Metal exploration towards the 1 nm Node

Gupta, Anshul; Radisic, Dunja; Maes, J.W.; Varela Pedreira, Olalla; Soulie, Jean-Philippe; Jourdan, Nicolas; Mertens, Hans; Bandyopadhyay, Sudip; Le, Quoc Toan; Pacco, Antoine; Heylen, Nancy; Vandersmissen, Kevin; Devriendt, Katia; Zhu, C.; Datta, S.; Sebaai, Farid; Wang, S.; Mousa, M.; Lee, J.; Geypen, Jef; De Wachter, Bart; Chehab, Bilal; Salahuddin, Shairfe Muhammad; Murdoch, Gayle; Biesemans, Serge; Tokei, Zsolt; Dentoni Litta, Eugenio; Horiguchi, Naoto (2021)

Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond

Gupta, Anshul; Varela Pedreira, Olalla; Tao, Zheng; Mertens, Hans; Radisic, Dunja; Jourdan, Nicolas; Devriendt, Katia; Heylen, Nancy; Wang, Shouhua; Chehab, Bilal; Jang, Doyoung; Hellings, Geert; Sebaai, Farid; Lorant, Christophe; Teugels, Lieve; Peter, Antony; Chan, BT; Schleicher, Filip; Demonie, Ingrid; Marien, Philippe; Sepulveda Marquez, Alfonso; Richard, Olivier; Nagesh, Nishanth; Lesniewska, Alicja; Lazzarino, Frederic; Ryckaert, Julien; Morin, Pierre; Altamirano Sanchez, Efrain; Murdoch, Gayle; Boemmels, Juergen; Demuynck, Steven; Na, Myung Hee; Tokei, Zsolt; Biesemans, Serge; Dentoni Litta, Eugenio; Horiguchi, Naoto (2020)

Buried power rails and back-side power grids: ARM CPU power delivery network design beyond 5nm

Prasad, D.; Nibhanupudi, S.; Das, S.; Zografos, Odysseas; Chehab, Bilal; Sarkar, Satadru; Baert, Rogier; Robinson, A.; Gupta, Anshul; Spessot, Alessio; Debacker, Peter; Verkest, Diederik; Kulkarni, J.; Cline, B.; Sinha, S. (2019)

Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node

Chen, Rongmei; Sisto, Giuliano; Jourdain, Anne; Hiblot, Gaspard; Stucchi, Michele; Kakarla, Naveen; Chehab, Bilal; Salahuddin, Shairfe Muhammad; Schleicher, Filip; Veloso, Anabela; Hellings, Geert; Weckx, Pieter; Milojevic, Dragomir; Van der Plas, Geert; Ryckaert, Julien; Beyne, Eric (2021)

Design enablement of CFET devices for sub-2nm CMOS nodes

Zografos, Odysseas; Chehab, Bilal; Schuddinck, Pieter; Mirabelli, Gioele; Kakarla, Naveen; Xiang, Yang; Weckx, Pieter; Ryckaert, Julien (2022-05-19)

Design, patterning, and process integration overview for 2nm node

Sherazi, Yasser; Chang, Yi-Han; Drissi, Youssef; Chehab, Bilal; Vega Gonzalez, Victor; Kim, Ryan Ryoung Han; Lee, Jae Uk (2022)

Design-Technology Co-Optimization of Sequential and Monolithic CFET as enabler of technology node beyond 2nm

Chehab, Bilal; Ryckaert, Julien; Schuddinck, Pieter; Weckx, Pieter; Horiguchi, Naoto; Mirabelli, Gioele; Spessot, Alessio; Na, Myung Hee (2021)

Disruptive Technology Elements, and Rapid and Accurate Block-Level Performance Evaluation for 3nm and Beyond

Na, Myung Hee; Jang, Doyoung; Baert, Rogier; Sarkar, Satadru; Patli, Sudhir; Zografos, Odysseas; Chehab, Bilal; Spessot, Alessio; Sisto, Giuliano; Schuddinck, Pieter; Mertens, Hans; Oniki, Yusuke; Hellings, Geert; Dentoni Litta, Eugenio; Ryckaert, Julien; Horiguchi, Naoto (2021)

Enabling sub-5nm CMOS technology scaling thinner and taller!

Ryckaert, Julien; Na, Myung Hee; Weckx, Pieter; Jang, Doyoung; Schuddinck, Pieter; Chehab, Bilal; Patli, Sudhir; Sarkar, Satadru; Zografos, Odysseas; Baert, Rogier; Verkest, Diederik (2019)

Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3 nm Era

Sisto, Giuliano; Zografos, Odysseas; Chehab, Bilal; Kakarla, Naveen; Xiang, Yang; Milojevic, Dragomir; Weckx, Pieter; Hellings, Geert; Ryckaert, Julien (2022)

Extended Scale Length Theory Targeting Low-Dimensional FETs for Carbon Nanotube FET Digital Logic Design-Technology Co-optimization

Gilardi, C.; Chehab, Bilal; Sisto, Giuliano; Schuddinck, Pieter; Ahmed, Zuhaib; Zografos, Odysseas; Lin, Q.; Hellings, Geert; Ryckaert, Julien; Wong, H-S P.; Mitra, S. (2021)

Forksheet FETs for Advanced CMOS Scaling: Forksheet-Nanosheet Co-Integration and Dual Work Function Metal Gates at 17nm N-P Space

Mertens, Hans; Ritzenthaler, Romain; Oniki, Yusuke; Briggs, Basoene; Chan, BT; Hikavyy, Andriy; Hopf, Toby; Mannaert, Geert; Tao, Zheng; Sebaai, Farid; Peter, Antony; Vandersmissen, Kevin; Dupuy, Emmanuel; Rosseel, Erik; Batuk, Dmitry; Geypen, Jef; Martinez Alanis, Gerardo Tadeo; Abigail, Daniel_; Grieten, Eva; D'have, Koen; Mitard, Jerome; Subramanian, Sujith; Ragnarsson, Lars-Ake; Weckx, Pieter; Chehab, Bilal; Hellings, Geert; Ryckaert, Julien; Dentoni Litta, Eugenio; Horiguchi, Naoto (2021)