Browsing by author "Sebaai, Farid"

Now showing items 1-20 of 90

    • 12-EUV layer Surrounding Gate Transistor (SGT) for vertical 6-T SRAM: 5-nm-class technology for ultra-density logic devices 

      Kim, Min-Soo; Harada, N.; Kikuchi, Yoshiaki; Boemmels, Juergen; Mitard, Jerome; Huynh Bao, Trong; Matagne, Philippe; Tao, Zheng; Li, Waikin; Devriendt, Katia; Ragnarsson, Lars-Ake; Lorant, Christophe; Sebaai, Farid; Porret, Clément; Rosseel, Erik; Dangol, Anish; Batuk, Dmitry; Martinez Alanis, Gerardo Tadeo; Geypen, Jef; Jourdan, Nicolas; Sepulveda Marquez, Alfonso; Puliyalil, Harinarayanan; Jamieson, Geraldine; van der Veen, Marleen; Teugels, Lieve; El-Mekki, Zaid; Altamirano Sanchez, Efrain; Li, Y.; Nakamura, H.; Mocuta, Dan; Matsuoka, F. (2019)

    • 300 mm wafer development for pattern collapse evaluations 

      Xu, XiuMei; Tao, Zheng; Saib, Mohamed; Sebaai, Farid; Van de Kerkhove, Jeroen; Vrancken, Nandi; Vereecke, Guy; Holsteyns, Frank (2018)

    • A low-power HKMG CMOS platform compatible with DRAM node 2x and beyond 

      Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; Caillat, Christian; Aoulaiche, Marc; Cho, Moon Ju; Noh, Kyung Bong; Son, Yunik; Na, Hoon Jo; Kauerauf, Thomas; Douhard, Bastien; Nazir, Aftab; Chew, Soon Aik; Milenin, Alexey; Altamirano Sanchez, Efrain; Schoofs, Geert; Albert, Johan; Sebaai, Farid; Vecchio, Emma; Paraschiv, Vasile; Vandervorst, Wilfried; Lee, Sun Ghil; Collaert, Nadine; Fazan, Pierre; Horiguchi, Naoto; Thean, Aaron (2014)

    • A method to pattern tight tip-to-tip in 32nm-pitch N5 interconnect using Ru area selective deposition tone inversion process 

      Briggs, Basoene; Soethoudt, Job; Delabie, Annelies; Wilson, Chris; Tokei, Zsolt; Boemmels, Juergen; Devriendt, Katia; Sebaai, Farid; Lorant, Christophe; Hody, Hubert (2018)

    • A new method to fabricate Ge nanowires: selective lateral etching of GeSn:P-Ge multi-stacks 

      Porret, Clément; Vohra, Anurag; Sebaai, Farid; Douhard, Bastien; Hikavyy, Andriy; Loo, Roger (2018)

    • A Novel Ni-Al Alloy Metal Induced Lateral Crystallization Process for Improved Channel Conduction in 3-D NAND Flash 

      Ramesh, Siva; Banerjee, Kaustuv; Opsomer, Karl; Rachita, Iuliana; Bastos, Joao; Soulie, Jean-Philippe; Sebaai, Farid; Favia, Paola; Korytov, Maxim; Richard, Olivier; Breuil, Laurent; Arreghini, Antonio; Van den Bosch, Geert; Rosmeulen, Maarten (2022)

    • An in-depth study of high-performing strained germanium nanaowires pFETs 

      Mitard, Jerome; Jang, Doyoung; Eneman, Geert; Arimura, Hiroaki; Parvais, Bertrand; Richard, Olivier; Van Marcke, Patricia; Witters, Liesbeth; Capogreco, Elena; Bender, Hugo; Ritzenthaler, Romain; Mertens, Hans; Hikavyy, Andriy; Loo, Roger; Dekkers, Harold; Sebaai, Farid; Horiguchi, Naoto; Mocuta, Anda; Collaert, Nadine (2018)

    • An InGaAs/InP quantum well FinFET using the replacement fin process integrated in an RMG flow on 300mm Si substrates 

      Waldron, Niamh; Merckling, Clement; Guo, Weiming; Ong, Patrick; Teugels, Lieve; Ansar, Sheikh; Tsvetanova, Diana; Sebaai, Farid; van Dorp, Dennis; Milenin, Alexey; Lin, Dennis; Nyns, Laura; Mitard, Jerome; Pourghaderi, Mohammad Ali; Douhard, Bastien; Richard, Olivier; Bender, Hugo; Boccardi, Guillaume; Caymax, Matty; Heyns, Marc; Vandervorst, Wilfried; Barla, Kathy; Collaert, Nadine; Thean, Aaron (2014)

    • Buried Power Rail Integration for CMOS Scaling beyond the 3 nm Node 

      Gupta, Anshul; Tao, Zheng; Radisic, Dunja; Mertens, Hans; Varela Pedreira, Olalla; Demuynck, Steven; Boemmels, Juergen; Devriendt, Katia; Heylen, Nancy; Wang, Shouhua; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Subramanian, Sujith; Schleicher, Filip; Peter, Antony; Rassoul, Nouredine; Siew, Yong Kong; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; Capogreco, Elena; Mannaert, Geert; Sepulveda Marquez, Alfonso; Dupuy, Emmanuel; Vandersmissen, Kevin; Chehab, Bilal; Murdoch, Gayle; Altamirano Sanchez, Efrain; Biesemans, Serge; Tokei, Zsolt; Dentoni Litta, Eugenio; Horiguchi, Naoto (2022)

    • Buried power rail integration with FinFETs for ultimate CMOS scaling 

      Gupta, Anshul; Varela Pedreira, Olalla; Arutchelvan, Goutham; Zahedmanesh, Houman; Devriendt, Katia; Hanssen, Frederik; Tao, Zheng; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Dentoni Litta, Eugenio; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, Noemie; Sepulveda Marquez, Alfonso; Mertens, Sofie; Kim, Min-Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Cousserier, Joris; Yakimets, Dmitry; Lazzarino, Frederic; Chehab, Bilal; Favia, Paola; Drijbooms, Chris; Jaysankar, Manoj; Morin, Pierre; Altamirano Sanchez, Efrain; Mitard, Jerome; Wilson, Chris; Holsteyns, Frank; Boemmels, Juergen; Demuynck, Steven; Tokei, Zsolt; Horiguchi, Naoto (2020)

    • Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node 

      Gupta, Anshul; Mertens, Hans; Tao, Zheng; Demuynck, Steven; Boemmels, Juergen; Arutchelvan, Goutham; Devriendt, Katia; Varela Pedreira, Olalla; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Zahedmanesh, Houman; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Dentoni Litta, Eugenio; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, N.; Sepulveda Marquez, Alfonso; Mertens, Sofie; Kim, Min Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Yakimets, Dmitry; Chehab, Bilal; Favia, Paola; Drijbooms, Chris; Cousserier, Joris; Jaysankar, Manoj; Lazzarino, Frederic; Morin, Pierre; Altamirano Sanchez, Efrain; Mitard, Jerome; Wilson, Chris; Holsteyns, Frank; Tokei, Zsolt; Horiguchi, Naoto (2020)

    • Buried Power Rail Metal exploration towards the 1 nm Node 

      Gupta, Anshul; Radisic, Dunja; Maes, J.W.; Varela Pedreira, Olalla; Soulie, Jean-Philippe; Jourdan, Nicolas; Mertens, Hans; Bandyopadhyay, Sudip; Le, Quoc Toan; Pacco, Antoine; Heylen, Nancy; Vandersmissen, Kevin; Devriendt, Katia; Zhu, C.; Datta, S.; Sebaai, Farid; Wang, S.; Mousa, M.; Lee, J.; Geypen, Jef; De Wachter, Bart; Chehab, Bilal; Salahuddin, Shairfe Muhammad; Murdoch, Gayle; Biesemans, Serge; Tokei, Zsolt; Dentoni Litta, Eugenio; Horiguchi, Naoto (2021)

    • Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond 

      Gupta, Anshul; Varela Pedreira, Olalla; Tao, Zheng; Mertens, Hans; Radisic, Dunja; Jourdan, Nicolas; Devriendt, Katia; Heylen, Nancy; Wang, Shouhua; Chehab, Bilal; Jang, Doyoung; Hellings, Geert; Sebaai, Farid; Lorant, Christophe; Teugels, Lieve; Peter, Antony; Chan, BT; Schleicher, Filip; Demonie, Ingrid; Marien, Philippe; Sepulveda Marquez, Alfonso; Richard, Olivier; Nagesh, Nishanth; Lesniewska, Alicja; Lazzarino, Frederic; Ryckaert, Julien; Morin, Pierre; Altamirano Sanchez, Efrain; Murdoch, Gayle; Boemmels, Juergen; Demuynck, Steven; Na, Myung Hee; Tokei, Zsolt; Biesemans, Serge; Dentoni Litta, Eugenio; Horiguchi, Naoto (2020)

    • Challenges and solutions of replacement metal gate patterning to enable gate-all-around device scaling 

      Oniki, Yusuke; Ragnarsson, Lars-Ake; Hideaki, Iino; Cott, Daire; Chan, BT; Sebaai, Farid; Hopf, Toby; Dekkers, Harold; Dentoni Litta, Eugenio; Altamirano Sanchez, Efrain; Holsteyns, Frank; Horiguchi, Naoto (2021)

    • Challenges on surface conditioning in 3D device architectures: triple-gate FinFETs, gate-all-around lateral and vertical nanowire FETs 

      Veloso, Anabela; Paraschiv, Vasile; Vecchio, Emma; Devriendt, Katia; Li, Waikin; Simoen, Eddy; Chan, BT; Tao, Zheng; Rosseel, Erik; Loo, Roger; Milenin, Alexey; Kunert, Bernardette; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; van Dorp, Dennis; Altamirano Sanchez, Efrain; Brus, Stephan; Marien, Philippe; Fleischmann, Claudia; Melkonyan, Davit; Huynh Bao, Trong; Eneman, Geert; Hellings, Geert; Sibaja-Hernandez, Arturo; Matagne, Philippe; Waldron, Niamh; Mocuta, Dan; Collaert, Nadine (2017)

    • Challenges on surface conditioning in 3D device architectures: triple-gate finFETs, gate-all-around lateral and vertical nanowireFETs 

      Veloso, Anabela; Paraschiv, Vasile; Vecchio, Emma; Devriendt, Katia; Li, Waikin; Simoen, Eddy; Chan, BT; Tao, Zheng; Rosseel, Erik; Loo, Roger; Milenin, Alexey; Kunert, Bernardette; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; van Dorp, Dennis; Altamirano Sanchez, Efrain; Brus, Stephan; Marien, Philippe; Sibaja-Hernandez, Arturo; Matagne, Philippe; Waldron, Niamh; Mocuta, Dan; Collaert, Nadine (2017)

    • Cleaning and strip requirement for metal gate based CMOS integration 

      Schram, Tom; Sebaai, Farid; Claes, Martine; Vos, Rita; Wada, Masayuli; Rohr, Erika; Kubicek, Stefan (2009)

    • Cleaning and strip requirements for metal gate based CMOS integration 

      Schram, Tom; Sebaai, Farid; Claes, Martine; Vos, Rita; Wada, Masayuki; Albert, Johan; Rohr, Erika; Kubicek, Stefan (2009)

    • Cleaning the high aspect ratio STI structures for advanced logic devices by implementation of a surface modification drying technique 

      Sebaai, Farid; Vereecke, Guy; Xu, XiuMei; Baudot, Sylvain; Amemiya, Fumihiro; Komori, Kana; Holsteyns, Frank (2018)

    • CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits 

      Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O'Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto (2018)