Browsing by author "Mertens, Hans"

15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

Mitard, Jerome; Witters, Liesbeth; Loo, Roger; Lee, Seung Hun; Sun, J.W.; Franco, Jacopo; Ragnarsson, Lars-Ake; Brand, A.; Lu, X.; Yoshido, N.; Eneman, Geert; Brunco, David; Vorderwestner, M.; Storck, P.; Milenin, Alexey; Hikavyy, Andriy; Waldron, Niamh; Favia, Paola; Vanhaeren, Danielle; Vanderheyden, Annelies; Richard, Olivier; Mertens, Hans; Arimura, Hiroaki; Sioncke, Sonja; Vrancken, Christa; Bender, Hugo; Eyben, Pierre; Barla, Kathy; Lee, Sun Ghil; Horiguchi, Naoto; Collaert, Nadine; Thean, Aaron (2014)

3D FinFET gate etch for advanced CMOS scaling

Dupuy, Emmanuel; Altamirano Sanchez, Efrain; Marinov, Daniil; Hody, Hubert; Mertens, Hans; Siew, Yong Kong; Demuynck, Steven; Horiguchi, Naoto (2019)

3D-carrier profiling and parasitic resistance analysis in vertically stacked gate-all-around Si nanowire CMOS transistors

Eyben, Pierre; Ritzenthaler, Romain; De Keersgieter, An; Chiarella, Thomas; Veloso, Anabela; Mertens, Hans; Pena, Vanessa; Santoro, Gaetano; Machillot, Jerome; Kim, Myungsun; Miyashita, Toshihiko; Yoshida, Naomi; Bender, Hugo; Richard, Olivier; Celano, Umberto; Paredis, Kristof; Wouters, Lennaert; Mitard, Jerome; Horiguchi, Naoto (2019)

A 2nd generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si-channel FinFETs

Mitard, Jerome; Witters, Liesbeth; Sasaki, Yuichiro; Arimura, Hiroaki; Schulze, Andreas; Loo, Roger; Ragnarsson, Lars-Ake; Hikavyy, Andriy; Cott, Daire; Chiarella, Thomas; Kubicek, Stefan; Mertens, Hans; Ritzenthaler, Romain; Vrancken, Christa; Favia, Paola; Bender, Hugo; Horiguchi, Naoto; Barla, Kathy; Mocuta, Dan; Mocuta, Anda; Collaert, Nadine; Thean, Aaron (2016-06)

An in-depth study of high-performing strained germanium nanaowires pFETs

Mitard, Jerome; Jang, Doyoung; Eneman, Geert; Arimura, Hiroaki; Parvais, Bertrand; Richard, Olivier; Van Marcke, Patricia; Witters, Liesbeth; Capogreco, Elena; Bender, Hugo; Ritzenthaler, Romain; Mertens, Hans; Hikavyy, Andriy; Loo, Roger; Dekkers, Harold; Sebaai, Farid; Horiguchi, Naoto; Mocuta, Anda; Collaert, Nadine (2018)

Application of group IV epitaxy for production of gate all around transistors

Hikavyy, Andriy; Mertens, Hans; Witters, Liesbeth; Loo, Roger; Horiguchi, Naoto (2017)

BTI reliability and time-dependent variability of stacked gate-all-around Si nanowire transistors

Vaisman Chasin, Adrian; Franco, Jacopo; Kaczer, Ben; Putcha, Vamsi; Weckx, Pieter; Ritzenthaler, Romain; Mertens, Hans; Horiguchi, Naoto; Linten, Dimitri; Rzepa, Gerhard (2017)

BTI reliability of advanced gate stacks for beyond silicon devices: challenges and opportunities

Groeseneken, Guido; Franco, Jacopo; Cho, Moon Ju; Kaczer, Ben; Toledano Luque, Maria; Roussel, Philippe; Kauerauf, Thomas; Alian, AliReza; Mitard, Jerome; Arimura, Hiroaki; Lin, Dennis; Waldron, Niamh; Sioncke, Sonja; Witters, Liesbeth; Mertens, Hans; Ragnarsson, Lars-Ake; Heyns, Marc; Collaert, Nadine; Thean, Aaron; Steegen, An (2014-12)

Buried Power Rail Integration for CMOS Scaling beyond the 3 nm Node

Gupta, Anshul; Tao, Zheng; Radisic, Dunja; Mertens, Hans; Varela Pedreira, Olalla; Demuynck, Steven; Boemmels, Juergen; Devriendt, Katia; Heylen, Nancy; Wang, Shouhua; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Subramanian, Sujith; Schleicher, Filip; Peter, Antony; Rassoul, Nouredine; Siew, Yong Kong; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; Capogreco, Elena; Mannaert, Geert; Sepulveda Marquez, Alfonso; Dupuy, Emmanuel; Vandersmissen, Kevin; Chehab, Bilal; Murdoch, Gayle; Altamirano Sanchez, Efrain; Biesemans, Serge; Tokei, Zsolt; Dentoni Litta, Eugenio; Horiguchi, Naoto (2022)

Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node

Gupta, Anshul; Mertens, Hans; Tao, Zheng; Demuynck, Steven; Boemmels, Juergen; Arutchelvan, Goutham; Devriendt, Katia; Varela Pedreira, Olalla; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Zahedmanesh, Houman; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Dentoni Litta, Eugenio; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, N.; Sepulveda Marquez, Alfonso; Mertens, Sofie; Kim, Min Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Yakimets, Dmitry; Chehab, Bilal; Favia, Paola; Drijbooms, Chris; Cousserier, Joris; Jaysankar, Manoj; Lazzarino, Frederic; Morin, Pierre; Altamirano Sanchez, Efrain; Mitard, Jerome; Wilson, Chris; Holsteyns, Frank; Tokei, Zsolt; Horiguchi, Naoto (2020)

Buried Power Rail Metal exploration towards the 1 nm Node

Gupta, Anshul; Radisic, Dunja; Maes, J.W.; Varela Pedreira, Olalla; Soulie, Jean-Philippe; Jourdan, Nicolas; Mertens, Hans; Bandyopadhyay, Sudip; Le, Quoc Toan; Pacco, Antoine; Heylen, Nancy; Vandersmissen, Kevin; Devriendt, Katia; Zhu, C.; Datta, S.; Sebaai, Farid; Wang, S.; Mousa, M.; Lee, J.; Geypen, Jef; De Wachter, Bart; Chehab, Bilal; Salahuddin, Shairfe Muhammad; Murdoch, Gayle; Biesemans, Serge; Tokei, Zsolt; Dentoni Litta, Eugenio; Horiguchi, Naoto (2021)

Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond

Gupta, Anshul; Varela Pedreira, Olalla; Tao, Zheng; Mertens, Hans; Radisic, Dunja; Jourdan, Nicolas; Devriendt, Katia; Heylen, Nancy; Wang, Shouhua; Chehab, Bilal; Jang, Doyoung; Hellings, Geert; Sebaai, Farid; Lorant, Christophe; Teugels, Lieve; Peter, Antony; Chan, BT; Schleicher, Filip; Demonie, Ingrid; Marien, Philippe; Sepulveda Marquez, Alfonso; Richard, Olivier; Nagesh, Nishanth; Lesniewska, Alicja; Lazzarino, Frederic; Ryckaert, Julien; Morin, Pierre; Altamirano Sanchez, Efrain; Murdoch, Gayle; Boemmels, Juergen; Demuynck, Steven; Na, Myung Hee; Tokei, Zsolt; Biesemans, Serge; Dentoni Litta, Eugenio; Horiguchi, Naoto (2020)

CDM-time domain turn-on transient of ESD diodes in bulk FinFET and GAA NW technologies

Chen, Shih-Hung; Linten, Dimitri; Hellings, Geert; Simicic, Marko; Kaczer, Ben; Chiarella, Thomas; Mertens, Hans; Mitard, Jerome; Mocuta, Anda; Horiguchi, Naoto (2019)

CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark

Liu, Hsiao-Hsuan; Schuddinck, Pieter; Pei, Zhenlin; Verschueren, Lynn; Mertens, Hans; Salahuddin, Shairfe Muhammad; Hiblot, Gaspard; Xiang, Yang; Chan, Boon Teik; Subramanian, Sujith; Weckx, Pieter; Hellings, Geert; Garcia Bardon, Marie; Ryckaert, Julien; Pan, Chenyun; Catthoor, Francky (2023)

Challenges and progresses in high-k metal gate for Silicon-based advanced CMOS transistor architecture

Horiguchi, Naoto; Ragnarsson, Lars-Ake; Mertens, Hans; Arimura, Hiroaki; Ritzenthaler, Romain; Franco, Jacopo; Schram, Tom; Dekkers, Harold; Barla, Kathy; Mocuta, Dan (2017)

Challenges for I/O towards the 3-nm node: Si/SiGe superlatttice I/O finFET in a horizontal nanowire technology and the increased ausceptibility of bulk finFET technology to single event latchup

Hellings, Geert; Mertens, Hans; Karp, James; Maillard, Pierre; Subirats, Alexandre; Simoen, Eddy; Schram, Tom; Ragnarsson, Lars-Ake; Simicic, Marko; Chen, Shih-Hung; Parvais, Bertrand; Boudier, D; Cretu, B; Machillot, J; Pena, V; Sun, S; Yoshida, N; Kim, N; Mocuta, Anda; Linten, Dimitri; Hart, Michael; Horiguchi, Naoto (2018)