Browsing by author "Siew, Yong Kong"

Now showing items 1-20 of 38

    • 1/f noise in fully integrated electrolytically gated FinFETs with fin width down to 20nm 

      Martens, Koen; Du Bois, Bert; Van Roy, Wim; Severi, Simone; Siew, Yong Kong; Gupta, Anshul; Dupuy, Emmanuel; Radisic, Dunja; Altamirano Sanchez, Efrain; Simoen, Eddy (2019)

    • 3D FinFET gate etch for advanced CMOS scaling 

      Dupuy, Emmanuel; Altamirano Sanchez, Efrain; Marinov, Daniil; Hody, Hubert; Mertens, Hans; Siew, Yong Kong; Demuynck, Steven; Horiguchi, Naoto (2019)

    • Alternative metals for advanced interconnects 

      Adelmann, Christoph; Wen, Liang Gong; Peter, Antony; Siew, Yong Kong; Croes, Kristof; Swerts, Johan; Popovici, Mihaela Ioana; Sankaran, Kiroubanand; Pourtois, Geoffrey; Van Elshocht, Sven; Boemmels, Juergen; Tokei, Zsolt (2014)

    • Alternative metals for advanced interconnects 

      Adelmann, Christoph; Wen, Liang Gong; Peter, Antony; Siew, Yong Kong; Dutta, Shibesh; Croes, Kristof; Swerts, Johan; Popovici, Mihaela Ioana; Sankaran, Kiroubanand; Pourtois, Geoffrey; Van Elshocht, Sven; Boemmels, Juergen; Tokei, Zsolt (2014-10)

    • Buried Power Rail Integration for CMOS Scaling beyond the 3 nm Node 

      Gupta, Anshul; Tao, Zheng; Radisic, Dunja; Mertens, Hans; Varela Pedreira, Olalla; Demuynck, Steven; Boemmels, Juergen; Devriendt, Katia; Heylen, Nancy; Wang, Shouhua; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Subramanian, Sujith; Schleicher, Filip; Peter, Antony; Rassoul, Nouredine; Siew, Yong Kong; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; Capogreco, Elena; Mannaert, Geert; Sepulveda Marquez, Alfonso; Dupuy, Emmanuel; Vandersmissen, Kevin; Chehab, Bilal; Murdoch, Gayle; Altamirano Sanchez, Efrain; Biesemans, Serge; Tokei, Zsolt; Dentoni Litta, Eugenio; Horiguchi, Naoto (2022)

    • Buried power rail integration with FinFETs for ultimate CMOS scaling 

      Gupta, Anshul; Varela Pedreira, Olalla; Arutchelvan, Goutham; Zahedmanesh, Houman; Devriendt, Katia; Hanssen, Frederik; Tao, Zheng; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Dentoni Litta, Eugenio; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, Noemie; Sepulveda Marquez, Alfonso; Mertens, Sofie; Kim, Min-Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Cousserier, Joris; Yakimets, Dmitry; Lazzarino, Frederic; Chehab, Bilal; Favia, Paola; Drijbooms, Chris; Jaysankar, Manoj; Morin, Pierre; Altamirano Sanchez, Efrain; Mitard, Jerome; Wilson, Chris; Holsteyns, Frank; Boemmels, Juergen; Demuynck, Steven; Tokei, Zsolt; Horiguchi, Naoto (2020)

    • Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node 

      Gupta, Anshul; Mertens, Hans; Tao, Zheng; Demuynck, Steven; Boemmels, Juergen; Arutchelvan, Goutham; Devriendt, Katia; Varela Pedreira, Olalla; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Zahedmanesh, Houman; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Dentoni Litta, Eugenio; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, N.; Sepulveda Marquez, Alfonso; Mertens, Sofie; Kim, Min Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Yakimets, Dmitry; Chehab, Bilal; Favia, Paola; Drijbooms, Chris; Cousserier, Joris; Jaysankar, Manoj; Lazzarino, Frederic; Morin, Pierre; Altamirano Sanchez, Efrain; Mitard, Jerome; Wilson, Chris; Holsteyns, Frank; Tokei, Zsolt; Horiguchi, Naoto (2020)

    • Challenges for scaled damascene interconnects 

      Armini, Silvia; Swerts, Johan; Siew, Yong Kong; Vereecken, Philippe; Boemmels, Juergen; Struyf, Herbert; Tokei, Zsolt (2013)

    • Copper electromigration failure times evaluated over a wide range of voiding phases 

      Li, Yunlong; Croes, Kristof; Kirimura, Tomoyuki; Siew, Yong Kong; Tokei, Zsolt (2012)

    • Cu wire resistance improvement using Mn-based self-formed barriers 

      Siew, Yong Kong; Jourdan, Nicolas; Ciofi, Ivan; Croes, Kristof; Wilson, Chris; Tang, Baojun; Demuynck, Steven; Ai, Huang; Cellier, Daniel; Cockburn, Andrew; Boemmels, Juergen; Tokei, Zsolt (2014)

    • CVD Mn-based self-formed barrier for advanced interconnect technology 

      Siew, Yong Kong; Jourdan, Nicolas; Barbarin, Yohan; Machillot, Jerome; Demuynck, Steven; Croes, Kristof; Tseng, J.; Ai, Hua; Tang, Jing; Naik, M.; Wang, P.; Narasimhan, M.; Abraham, M.; Cockburn, Andrew; Boemmels, Juergen; Tokei, Zsolt (2013)

    • CVD-Mn(Nx) as copper diffusion barrier for advanced interconnect technologies 

      Jourdan, Nicolas; Machillot, Jerome; Barbarin, Yohan; Siew, Yong Kong; Ai, Hua; Cockburn, Andrew; Nguyen, Mai Phuong; Van Elshocht, Sven; Boemmels, Juergen; Lakshmanan, A.; Ma, Paul; Narasimhan, Murali; Tokei, Zsolt (2013)

    • Dry etch challenges in a 20 nm half-pitch single damascene spacer-defined patterning scheme 

      Kunnen, Eddy; Versluijs, Janko; Alaerts, Wilfried; Siew, Yong Kong; Struyf, Herbert; Beyer, Gerald (2010)

    • Electromigration-driven void nucleation and growth in 30nm wide Cu line: Metal cap impact on interfacial Cu diffusion 

      Kirimura, Tomoyuki; Croes, Kristof; Siew, Yong Kong; Vanstreels, Kris; Czarnecki, Piotr; El-Mekki, Zaid; van der Veen, Marleen; Dictus, Dries; Yoon, A.; Kolics, A.; Boemmels, Juergen; Tokei, Zsolt (2013)

    • Enabling interconnect scaling with spacer-defined double patterning (SDDP) 

      Siew, Yong Kong; Stucchi, Michele; Versluijs, Janko; Roussel, Philippe; Kunnen, Eddy; Pantouvaki, Marianna; Beyer, Gerald; Tokei, Zsolt (2013)

    • Enabling sub 20nm Cu metallization with PEALD Ru-TiN barrier and ELD seed 

      Siew, Yong Kong; Swerts, Johan; Dictus, Dries; El-Mekki, Zaid; Armini, Silvia; Dordi, Yezdi; Yoon, Alex; Kolics, Artur; Barbarin, Yohan; Croes, Kristof; Boemmels, Juergen; Tokei, Zsolt (2012)

    • Evaluation of Mn-based Cu barriers for interconnect applications 

      Van Besien, Els; Jourdan, Nicolas; Zhao, Larry; Croes, Kristof; Siew, Yong Kong; Van Elshocht, Sven; Tokei, Zsolt (2011)

    • Evaluation of the accuracy and precision of STEM and EDS metrology on horizontal GAA nanowire devices 

      Johanesen, Hayley; Strauss, Michael; Kenslea, Anne; Hakala, Chris; Kwakman, Laurens; Boullart, Werner; Mertens, Hans; Siew, Yong Kong; Barla, Kathy (2019)

    • Evaluation of wet Cu seed deposition to enable downscaling damascene metallization 

      Armini, Silvia; Li, Muyang; Swerts, Johan; Siew, Yong Kong; Caluwaerts, Rudy; Meersschaut, Johan; Franquet, Alexis; Moussa, Alain; Leunissen, Peter (2012)

    • First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers 

      Subramanian, Sujith; Hosseini, Maryam; Chiarella, Thomas; Sarkar, Satadru; Schuddinck, Pieter; Chan, BT; Radisic, Dunja; Mannaert, Geert; Hikavyy, Andriy; Rosseel, Erik; Sebaai, Farid; Peter, Antony; Hopf, Toby; Morin, Pierre; Wang, Shouhua; Devriendt, Katia; Batuk, Dmitry; Martinez Alanis, Gerardo Tadeo; Veloso, Anabela; Dentoni Litta, Eugenio; Baudot, Sylvain; Siew, Yong Kong; Zhou, X.; Briggs, Basoene; Capogreco, Elena; Hung, Joey; Koret, R.; Spessot, Alessio; Ryckaert, Julien; Demuynck, Steven; Horiguchi, Naoto; Boemmels, Juergen (2020)