Browsing by author "Gupta, Anshul"

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    • 1/f noise in fully integrated electrolytically gated FinFETs with fin width down to 20nm 

      Martens, Koen; Du Bois, Bert; Van Roy, Wim; Severi, Simone; Siew, Yong Kong; Gupta, Anshul; Dupuy, Emmanuel; Radisic, Dunja; Altamirano Sanchez, Efrain; Simoen, Eddy (2019)

    • A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology Nodes 

      Nibhanupudi, S. S. Teja; Prasad, Divya; Das, Shidhartha; Zografos, Odysseas; Robinson, Alex; Gupta, Anshul; Spessot, Alessio; Debacker, Peter; Verkest, Diederik; Ryckaert, Julien; Hellings, Geert; Myers, James; Cline, Brian; Kulkarni, Jaydeep P. (2022-07-07)

    • Alternative metals: from ab initio screening to calibrated narrow line models 

      Adelmann, Christoph; Sankaran, Kiroubanand; Dutta, Shibesh; Gupta, Anshul; Kundu, Shreya; Jamieson, Geraldine; Moors, Kristof; Pinna, Nicolo; Ciofi, Ivan; Van Elshocht, Sven; Boemmels, Juergen; Boccardi, Guillaume; Wilson, Chris; Pourtois, Geoffrey; Tokei, Zsolt (2018)

    • Buried Bitline for sub-5nm SRAM Design 

      Mathur, R.; Bhargava, M.; Annamalai, S.; Chong, Y. K.; Sinha, S.; Cline, B.; Kulkarni, J. P.; Salahuddin, Shairfe Muhammad; Schuddinck, Pieter; Ryckaert, Julien; Gupta, Anshul (2020)

    • Buried Interconnects for Sub-5 nm SRAM Design 

      Mathur, R.; Bhargava, M.; Cline, B.; Salahuddin, Shairfe Muhammad; Gupta, Anshul; Schuddinck, Pieter; Ryckaert, Julien; Kulkarni, J.P. (2022)

    • Buried Power Rail Integration for CMOS Scaling beyond the 3 nm Node 

      Gupta, Anshul; Tao, Zheng; Radisic, Dunja; Mertens, Hans; Varela Pedreira, Olalla; Demuynck, Steven; Boemmels, Juergen; Devriendt, Katia; Heylen, Nancy; Wang, Shouhua; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Subramanian, Sujith; Schleicher, Filip; Peter, Antony; Rassoul, Nouredine; Siew, Yong Kong; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; Capogreco, Elena; Mannaert, Geert; Sepulveda Marquez, Alfonso; Dupuy, Emmanuel; Vandersmissen, Kevin; Chehab, Bilal; Murdoch, Gayle; Altamirano Sanchez, Efrain; Biesemans, Serge; Tokei, Zsolt; Dentoni Litta, Eugenio; Horiguchi, Naoto (2022)

    • Buried power rail integration with FinFETs for ultimate CMOS scaling 

      Gupta, Anshul; Varela Pedreira, Olalla; Arutchelvan, Goutham; Zahedmanesh, Houman; Devriendt, Katia; Hanssen, Frederik; Tao, Zheng; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Dentoni Litta, Eugenio; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, Noemie; Sepulveda Marquez, Alfonso; Mertens, Sofie; Kim, Min-Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Cousserier, Joris; Yakimets, Dmitry; Lazzarino, Frederic; Chehab, Bilal; Favia, Paola; Drijbooms, Chris; Jaysankar, Manoj; Morin, Pierre; Altamirano Sanchez, Efrain; Mitard, Jerome; Wilson, Chris; Holsteyns, Frank; Boemmels, Juergen; Demuynck, Steven; Tokei, Zsolt; Horiguchi, Naoto (2020)

    • Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node 

      Gupta, Anshul; Mertens, Hans; Tao, Zheng; Demuynck, Steven; Boemmels, Juergen; Arutchelvan, Goutham; Devriendt, Katia; Varela Pedreira, Olalla; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Zahedmanesh, Houman; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Dentoni Litta, Eugenio; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, N.; Sepulveda Marquez, Alfonso; Mertens, Sofie; Kim, Min Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Yakimets, Dmitry; Chehab, Bilal; Favia, Paola; Drijbooms, Chris; Cousserier, Joris; Jaysankar, Manoj; Lazzarino, Frederic; Morin, Pierre; Altamirano Sanchez, Efrain; Mitard, Jerome; Wilson, Chris; Holsteyns, Frank; Tokei, Zsolt; Horiguchi, Naoto (2020)

    • Buried Power Rail Metal exploration towards the 1 nm Node 

      Gupta, Anshul; Radisic, Dunja; Maes, J.W.; Varela Pedreira, Olalla; Soulie, Jean-Philippe; Jourdan, Nicolas; Mertens, Hans; Bandyopadhyay, Sudip; Le, Quoc Toan; Pacco, Antoine; Heylen, Nancy; Vandersmissen, Kevin; Devriendt, Katia; Zhu, C.; Datta, S.; Sebaai, Farid; Wang, S.; Mousa, M.; Lee, J.; Geypen, Jef; De Wachter, Bart; Chehab, Bilal; Salahuddin, Shairfe Muhammad; Murdoch, Gayle; Biesemans, Serge; Tokei, Zsolt; Dentoni Litta, Eugenio; Horiguchi, Naoto (2021)

    • Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond 

      Gupta, Anshul; Varela Pedreira, Olalla; Tao, Zheng; Mertens, Hans; Radisic, Dunja; Jourdan, Nicolas; Devriendt, Katia; Heylen, Nancy; Wang, Shouhua; Chehab, Bilal; Jang, Doyoung; Hellings, Geert; Sebaai, Farid; Lorant, Christophe; Teugels, Lieve; Peter, Antony; Chan, BT; Schleicher, Filip; Demonie, Ingrid; Marien, Philippe; Sepulveda Marquez, Alfonso; Richard, Olivier; Nagesh, Nishanth; Lesniewska, Alicja; Lazzarino, Frederic; Ryckaert, Julien; Morin, Pierre; Altamirano Sanchez, Efrain; Murdoch, Gayle; Boemmels, Juergen; Demuynck, Steven; Na, Myung Hee; Tokei, Zsolt; Biesemans, Serge; Dentoni Litta, Eugenio; Horiguchi, Naoto (2020)

    • Buried power rails and back-side power grids: ARM CPU power delivery network design beyond 5nm 

      Prasad, D.; Nibhanupudi, S.; Das, S.; Zografos, Odysseas; Chehab, Bilal; Sarkar, Satadru; Baert, Rogier; Robinson, A.; Gupta, Anshul; Spessot, Alessio; Debacker, Peter; Verkest, Diederik; Kulkarni, J.; Cline, B.; Sinha, S. (2019)

    • Buried power SRAM DTCO and system-level benchmarking in N3 

      Salahuddin, Shairfe Muhammad; Perumkunnil, Manu; Dentoni Litta, Eugenio; Gupta, Anshul; Weckx, Pieter; Ryckaert, Julien; Na, Myung Hee; Spessot, Alessio (2020)

    • Challenges with SOT-MRAM integration towards N5 node and beyond 

      Gupta, Mohit; Perumkunnil, Manu; Yasin, Farrukh; Mirabelli, Gioele; Garello, K.; Gupta, Anshul; Furnemont, Arnaud; Kar, Gouri Sankar (2022)

    • Characterization and modeling of hot carrier degradation in N-channel gate-all-around nanowire FETs 

      Gupta, Charu; Gupta, Anshul; Tuli, Shikhar; Bury, Erik; Parvais, Bertrand; Dixit, Abhisek (2020)

    • CMOS area scaling and the need for high aspect ratio vias 

      Briggs, Basoene; Guissi, Sofiane; Wilson, Chris; Ryckaert, Julien; Paolillo, Sara; Vandersmissen, Kevin; Versluijs, Janko; Lorant, Christophe; Heylen, Nancy; Boemmels, Juergen; Tokei, Zsolt; Sherazi, Yasser; Weckx, Pieter; Kljucar, Luka; van der Veen, Marleen; Boccardi, Guillaume; De Heyn, Vincent; Gupta, Anshul; Ervin, Joseph; Kamon, Matt (2018)

    • Device-, circuit- & block-level evaluation of CFET in a 4 track library 

      Schuddinck, Pieter; Zografos, Odysseas; Weckx, Pieter; Matagne, Philippe; Sarkar, Satadru; Sherazi, Yasser; Baert, Rogier; Jang, Doyoung; Yakimets, Dmitry; Gupta, Anshul; Parvais, Bertrand; Ryckaert, Julien; Verkest, Diederik; Mocuta, Anda (2019)

    • Direct metal nanowire patterning using ion beam etch 

      Kundu, Shreya; Dutta, Shibesh; Gupta, Anshul; Jamieson, Geraldine; Piumi, Daniele; Boemmels, Juergen; Wilson, Chris; Tokei, Zsolt; Adelmann, Christoph (2017)

    • Engineering high quality and conformal ultrathin SiNx films by PEALD for downscaled and advanced CMOS nodes 

      Tomomi, Takayama; Taishi, Ebisudani; Eiichiro, Shiba; Sepulveda Marquez, Alfonso; Blanquart, Timothee; Kimura, Yosuke; Subramanian, Sujith; Baudot, Sylvain; Briggs, Basoene; Gupta, Anshul; Veloso, Anabela; Capogreco, Elena; Mertens, Hans; Meersschaut, Johan; Conard, Thierry; Dara, Praveen; Geypen, Jef; Martinez Alanis, Gerardo Tadeo; Batuk, Dmitry; Demuynck, Steven; Morin, Pierre (2021)

    • Extending the roadmap beyond 3nm through system scaling boosters: A case study on buried power rail and backside power delivery 

      Ryckaert, Julien; Gupta, Anshul; Jourdain, Anne; Chava, Bharani; Van der Plas, Geert; Verkest, Diederik; Beyne, Eric (2019)

    • High-aspect-ratio ruthenium lnes for buried power rail 

      Gupta, Anshul; Kundu, Shreya; Teugels, Lieve; Boemmels, Juergen; Adelmann, Christoph; Heylen, Nancy; Jamieson, Geraldine; Varela Pedreira, Olalla; Ciofi, Ivan; Chava, Bharani; Wilson, Chris; Tokei, Zsolt (2018)