In-line Metrology for Vertical Edge Placement Control of Monolithic CFET using CD-SEM

Abstract

The transistor architecture of complementary FET (CFET) is attractive for scaling down in technology nodes beyond 1 nm. CFET comprising vertically stacked nMOS and pMOS can be integrated monolithically and sequentially. The monolithic process is cost effective but complex because it requires patterning of high-aspect-ratio (HAR) structures and vertical edge placement control for stacked n-p nanosheet channels. It also brings challenges to in-line metrology in measuring the vertical dimension. In this work, we demonstrate a non-destructive, in-line metrology solution to measure the etch-back depth by CD-SEM. As the backscattered electron (BSE) signal intensity at the bottom of an HAR structure is determined by the structure's depth and top dimension, the depth can be monitored via an index based on the grey level and top dimension in CD-SEM images. Wafers with different etch-back depths were measured for evaluation of the M0 etch-back process in CFET integration. Good agreement was obtained between the etch-back depths measured by CD-SEM and TEM. The flexible capability of CD-SEM to measure the depth and variation from extremely small areas to the wafer level could be helpful for CFET process control.