Where to apply sustainability optimizations in process flows?

Abstract

Future advanced semiconductor manufacturing processes are introducing significant patterning challenges. These challenges are coming together with additional requirements for sustainable, low Global Warming Potential/ low toxicity /low fine particle emissions. As a result, new solutions in terms of process integrations, molecules used for patterning modules, and overall stack of materials will have to meet those requirements while staying compatible with high-volume manufacturing (cost, availability, throughput, and overall patterning performance). Although specific process steps such as capacitor patterning for DRAM or 3D NAND high aspect ratio oxide etch are heavily scrutinized steps in terms of emissions and patterning challenges, many applications, including logic, integrate hundreds of steps where the patterning of 10-30 nm-thick layers requiring fluorine-containing gases. Although independently accounting for a modest amount of emissions, their sheer counts makes them a major contributor to CO2 equivalent emissions. In this work, the cumulative impact of these low aspect-ratio patterning steps will be modelled through the imec.netzero program model. Then, the impact of a few sustainability-optimized solutions, such as low temperature etching for ultra-thin layer or stack optimization will be assessed.