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dc.contributor.authorKim, Woojin
dc.contributor.authorPica, Valerio
dc.contributor.authorJossart, Nico
dc.contributor.authorYasin, Farrukh
dc.contributor.authorWostyn, Kurt
dc.contributor.authorCouet, Sebastien
dc.contributor.authorRao, Siddharth
dc.date.accessioned2024-11-14T12:45:24Z
dc.date.available2024-07-12T18:43:09Z
dc.date.available2024-11-14T12:45:24Z
dc.date.issued2024
dc.identifier.issn2330-7978
dc.identifier.otherWOS:001233896700014
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/44150.2
dc.sourceWOS
dc.titleA novel test and analysis scheme to elucidate tail bit characteristics in STT-MRAM arrays
dc.typeProceedings paper
dc.contributor.imecauthorKim, Woojin
dc.contributor.imecauthorPica, Valerio
dc.contributor.imecauthorJossart, Nico
dc.contributor.imecauthorYasin, Farrukh
dc.contributor.imecauthorWostyn, Kurt
dc.contributor.imecauthorCouet, Sebastien
dc.contributor.imecauthorRao, Siddharth
dc.contributor.orcidimecKim, Woojin::0000-0002-2755-6661
dc.contributor.orcidimecPica, Valerio::0009-0004-2468-4029
dc.contributor.orcidimecJossart, Nico::0009-0003-2798-8290
dc.contributor.orcidimecYasin, Farrukh::0000-0002-7295-0254
dc.contributor.orcidimecWostyn, Kurt::0000-0003-3995-0292
dc.contributor.orcidimecCouet, Sebastien::0000-0001-6436-9593
dc.contributor.orcidimecRao, Siddharth::0000-0001-6161-3052
dc.identifier.doi10.1109/IMW59701.2024.10536950
dc.identifier.eisbn979-8-3503-0652-1
dc.source.numberofpages4
dc.source.peerreviewyes
dc.source.conferenceInternational Memory Workshop (IMW)
dc.source.conferencedateMAY 12-15, 2024
dc.source.conferencelocationSeoul
dc.source.journalN/A
imec.availabilityPublished - imec
dc.description.wosFundingTextThis work is supported by IMEC's Industrial Affiliation Program on STT-MRAM devices. The authors would also like to acknowledge the support of imec's fab, line, MCA and hardware teams


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