A 200-256-GS/s Current-Mode 4-Way Interleaved Sampling Front-End With Over 67-GHz Bandwidth Using a Slew-Rate Insensitive Clocking Scheme

Abstract

The surge of data traffic in emerging optical communication applications has led to the development of ultra-fast transceivers with extremely high data throughput. The latest transmitters and receivers aim for symbol rates of 150-200 Gbaud or even higher, striving to achieve band-widths beyond 70 GHz. However, the current state-of-the-artanalog-to-digital converters (ADCs) in advanced CMOS-FinFET technologies can only handle limited analog input bandwidths and sampling rates, becoming a bottleneck in enhancing the overall speed of the transceiver. A time-interleaved sampling front-end acting as an input signal de-interleaver can reduce the sub-ADCs' analog bandwidth and clock jitter requirements. This article investigates a current-mode time-interleaved 1-4 sampling front-end operating at 200-256 GS/s, using a 50% duty-cycle slew-rate insensitive quadrature clocking strategy. The chip was fabricated in a 130-nm SiGe BiCMOS technology and was characterized by single-tone sinusoidal and non-return-to-zero/pulse-amplitude- modulation-4-level (NRZ/PAM-4)measurements at 200, 224, and 256 GS/s. The chip demonstratesa 3-dB analog input bandwidth beyond 67 GHz and a signal-to-noise-and-distortion ratio (SNDR) of 27.8-34.1 dB (at 200 GS/s),25-36.3 dB (at 224 GS/s), and 22.3-39 dB (at 256 GS/s) for input frequencies from 1.1 to 67.1 GHz. The analog demultiplexing functionality of the sampling front-end is demonstrated with 100,112, and 128 Gbaud NRZ/PAM-4 measurements. The completechip consumes a power of 1.1 W at 256 GS/s, corresponding to an efficiency of 4.3 pJ/sample or 4.3 pJ/bit (with two samplesper symbol).