Enhanced Infrared Imaging for Die-Level Fault Isolation Using Lock-In Thermography

Abstract

In this paper, we demonstrate three experimental approaches to improve the performance of lock-in thermography (LIT). The infrared imaging (IR) technique is extensively used for failure analysis (FA) in the semiconductor industry. However, with the conventional LIT, low-contrast topography images can be obtained at room temperature due to the poor emissivity gradient in the devices and the limitation on the performance of the infrared camera. The grayscale topographical contrast is improved significantly when the device under test is heated from room temperature to 90 degrees C. A compact printed circuit board heater is designed and customized for this application. Furthermore, the heater can also be used in the lock-in loop to get the enhanced topography images. These methods are implemented experimentally, and the results are validated using finite element simulation. The thermal enhancement approaches proposed in this paper are demonstrated at die level on a defective silicon interposer sample. The topographical contrast and the signal intensity of the hotspot obtained are enhanced when compared to the classical LIT performed at room temperature. To reduce the thermal budget of the heat-assisted method, dual LIT is developed where the two consecutive lock-in measurements are performed to obtain hotspot amplitude and topography image with good contrast. In addition, the topography image obtained from this technique is less susceptible to input noise levels. To increase the throughput of the FA process, quadrature lock-in thermography, a dual-purpose measurement technique is shown. A high-contrast topography image and the hotspot location are obtained from the same lock-in thermogram by performing trigonometric conditioning. The throughput from this approach is the same as the classical LIT technique.