Thermal Implications in Scaling High-Performance Server 3D Chiplet-based 2.5D SoC from FinFET to Nanosheet

Abstract

As heterogeneous integration gains momentum in high-performance server Systems-on-Chip, transitioning from traditional 2D architectures to 3D chiplet-based 2.5D configurations brings power and thermal management challenges. This paper models an integrated commercial high-performance server SoC in N7 (7nm) FinFET, projecting it into a 2D IO chiplet with Memory-on-Logic (MoL) and Logic-on-Memory (LoM) configurations of a 3D computing chiplet. This is coupled with functional simulation with the post-placement and post-routing (post-PnR) netlist and workload activity annotated power and thermal analysis in an advanced A14 (14 angstroms) Nanosheet CMOS technology, encompassing a holistic system technology co-optimization approach. Results demonstrate a transition from 2D to 3D chiplet-based 2.5D architectures, with a noteworthy 8.39%(N7) and 60.53%(A14) increase in temperature (celsius) concerning the technology under iso-die area considerations for chiplet-based configurations, and thermal analysis of MoL and LoM configurations indicate a maximum temperature rise difference of 5.55%. Furthermore, experimentation with various workloads unveils the complexity of thermal dynamics, exposing a temperature rise difference of up to 55.10%. This exploration underscores the necessity for thermal-aware design aligned with technology, workload, and system architecture considerations.