DTCO for Fast STT-MRAM Periphery Operation

Abstract

This manuscript presents a pioneering approach to Design-Technology Co-Optimization (DTCO) during the periphery design phase of Spin-Transfer Torque Magnetoresistive Random-Access Memory (STT-MRAM). By focusing on the intricate relationship between device geometry and its electrical and switching properties, our work co-optimizes both write and read periphery circuitries alongside with the required bit-cell. We introduce various circuit designs and thoroughly evaluate their performance across multiple processes, and voltage corners to ensure robustness and reliability. The optimized layout (commercial N22 PDK) ensures the accurate Power/Performance/Area (PPA) evaluation of the proposal. This comprehensive analysis not only sheds light on the trade-offs inherent in STT-MRAM periphery design but also paves the way for more efficient, reliable, and high-performance memory architectures. Through extensive simulation and characterization, we demonstrate how our co-optimization approach can significantly enhance the performance of STT-MRAM devices, achieving 15/0.5ns write/read respectively, and 1.6pJ/2.5fJ per bit operation, offering valuable insights for future memory system design.