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Investigations and physical modelling of saturation effects in lateral DMOS transistor architectures based on the concept of intrinsic drain voltage

dc.contributor.authorAnghel, C.
dc.contributor.authorHefyene, N.
dc.contributor.authorIonescu, A. M.
dc.contributor.authorVermandel, Miguel
dc.contributor.authorBakeroot, Benoit
dc.contributor.authorDoutrloigne, J.
dc.contributor.authorGillon, R.
dc.contributor.authorFrere, S.
dc.contributor.authorMaier., C.
dc.contributor.authorMourier, Y.
dc.date.accessioned2021-10-14T16:36:10Z
dc.date.available2021-10-14T16:36:10Z
dc.date.issued2001
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/5012
dc.sourceIIOimport
dc.titleInvestigations and physical modelling of saturation effects in lateral DMOS transistor architectures based on the concept of intrinsic drain voltage
dc.typeProceedings paper
dc.contributor.imecauthorBakeroot, Benoit
dc.contributor.orcidimecBakeroot, Benoit::0000-0003-4392-1777
dc.source.peerreviewno
dc.source.beginpage399
dc.source.endpage402
dc.source.conferenceProceedings of the 31st European Solid-State Device Research Conference
dc.source.conferencedate11/09/2001
dc.source.conferencelocationNuremberg Germany
imec.availabilityPublished - imec


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