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Investigations and physical modelling of saturation effects in lateral DMOS transistor architectures based on the concept of intrinsic drain voltage
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Investigations and physical modelling of saturation effects in lateral DMOS transistor architectures based on the concept of intrinsic drain voltage
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Date
2001
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Anghel, C.
;
Hefyene, N.
;
Ionescu, A. M.
;
Vermandel, Miguel
;
Bakeroot, Benoit
;
Doutrloigne, J.
;
Gillon, R.
;
Frere, S.
;
Maier., C.
;
Mourier, Y.
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1988
since deposited on 2021-10-14
Acq. date: 2025-12-09
Citations
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Views
1988
since deposited on 2021-10-14
Acq. date: 2025-12-09
Citations