Skip to content
Institutional repository
Communities & Collections
Browse
Site
Log In
Investigations and physical modelling of saturation effects in lateral DMOS transistor architectures based on the concept of intrinsic drain voltage
Statistics
Statistics by Category
Download view's map
PNG
JPEG/JPG
Reports
Most viewed
Most viewed per month
Top city views
File Visits
Export Excel
Export CSV
Item
Views
Investigations and physical modelling of saturation effects in lateral DMOS transistor architectures based on the concept of intrinsic drain voltage
1380