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Articles
Influence of gate length on ESD-performance for deep submicron CMOS technology
Publication:
Influence of gate length on ESD-performance for deep submicron CMOS technology
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Date
2001
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Bock, Karlheinz
;
Keppens, Bart
;
De Heyn, Vincent
;
Groeseneken, Guido
;
Ching, L. Y.
;
Naem, Abdalla
Journal
Microelectronics Reliability
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1889
since deposited on 2021-10-14
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Acq. date: 2025-12-10
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Metrics
Views
1889
since deposited on 2021-10-14
1
last month
Acq. date: 2025-12-10
Citations