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dc.contributor.authorCoen, G.
dc.contributor.authorDe Zutter, Daniel
dc.date.accessioned2021-09-29T13:04:38Z
dc.date.available2021-09-29T13:04:38Z
dc.date.issued1995
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/564
dc.sourceIIOimport
dc.titleReduction of circuit complexity by elimination of internal nodes in the circuit modeling of planar interconnection structures
dc.typeProceedings paper
dc.contributor.imecauthorDe Zutter, Daniel
dc.source.peerreviewno
dc.source.beginpage229
dc.source.endpage231
dc.source.conferenceElectrical Performance of Electronic Packaging; 2-4 Oct. 1995; Portland, OR, USA.
dc.source.conferencelocation
imec.availabilityPublished - imec


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