Reduction of circuit complexity by elimination of internal nodes in the circuit modeling of planar interconnection structures
dc.contributor.author | Coen, G. | |
dc.contributor.author | De Zutter, Daniel | |
dc.date.accessioned | 2021-09-29T13:04:38Z | |
dc.date.available | 2021-09-29T13:04:38Z | |
dc.date.issued | 1995 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/564 | |
dc.source | IIOimport | |
dc.title | Reduction of circuit complexity by elimination of internal nodes in the circuit modeling of planar interconnection structures | |
dc.type | Proceedings paper | |
dc.contributor.imecauthor | De Zutter, Daniel | |
dc.source.peerreview | no | |
dc.source.beginpage | 229 | |
dc.source.endpage | 231 | |
dc.source.conference | Electrical Performance of Electronic Packaging; 2-4 Oct. 1995; Portland, OR, USA. | |
dc.source.conferencelocation | ||
imec.availability | Published - imec |
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